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cy8cled04d01, CY8CLED04D02, cy8cled04g01 cy8cled03d01, cy8cled03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 powerpsoc ? intelligent led driver cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-46319 rev. *n revised may 4, 2011 powerpsoc intelligent led driver 1. features integrated power peripherals ? four internal 32 v low side n-channel power fets ?r ds(on) ? 0.5 ? for 1.0 a devices ? up to 2 mhz configurable switching frequency ? four hysteretic controllers ? independently programmable upper and lower thresholds ? programmable minimum on/off timers ? four low side gate drivers with programmable drive strength ? four precision high side current sense amplifiers ? three 16-bit led dimming modulators: prism, dmm, and pwm ? six fast response (100 ns) voltage comparators ? six 8-bit reference dacs ? built-in switching regulator eliminates external 5 v supply ? multiple topologies including floating load buck, floating load buck-boost, and boost m8c cpu core ? processor speeds up to 24 mhz advanced peripherals (psoc ? blocks) ? capacitive sensing application capability ? dmx512 interface ? i 2 c master or slave ? full-duplex uarts ? multiple spi masters or slaves ? integrated temperature sensor ? up to 12-bit adcs ? 6 to 12-bit incremental adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? 8 to 32-bit timers and counters ? complex peripherals by combining blocks ? configurable to all gpio pins programmable pin configurations ? 25 ma sink, 10 ma source on all gpio and func- tion pins ? pullup, pull down, high z, strong, or open drain drive modes on all gpio and function pins ? up to 10 analog inputs on gpio ? two 30 ma analog outputs on gpio ? configurable interrupt on all gpio flexible on-chip memory ? 16 k flash program storage 50,000 erase and write cycles ? 1 k sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software: psoc designer? ? full featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128 kbytes trace memory applications ? stage led lighting ? architectural led lighting ? general purpose led lighting ? automotive and emergency vehicle led lighting ? landscape led lighting ? display led lighting ? effects led lighting ? signage led lighting device options ? cy8cled04d0x ? four internal fets with 0.5 a and 1.0 a options ? four external gate drivers ? cy8cled04g01 ? four external gate drivers ? cy8cled03d0x ? three internal fets with 0.5 a and 1.0 a options ? three external gate drivers ? cy8cled03g01 ? three external gate drivers ? cy8cl ed02d01 ? two 1.0 a internal fets ? two external gate drivers ? cy8cled01d01 ? one 1.0 a internal fet ? one external gate driver 56-pin qfn package figure 1-1. powerpsoc architectural block diagram digital system analog system sram (1 k bytes) interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator ( ilo) global digital interconnect global analog interconnect 24 mhz internal main oscillator (imo) psoc core cpu core (m 8c) supervisory rom (srom) flash nonvolatile memory (1 6 k ) analog psoc block array analog ref i2c internal voltage reference digital clocks por and lvd system resets psoc system resources 2 analog columns io analog multiplexer system bus sc sc ct sc sc ct analog drivers port 0 macs (2) decimator (type 2) analog mux bus port 1 port 2 dbb 00 dbb 01 dcb 02 dcb 03 dbb 01 dbb 11 dcb 12 dcb13 digital psoc block array 2 digital rows system bus fn0 c1 c2 c3 c4 c5 c6 prism/ dmm / pwm logic core decoder analog block comparator bank dac bank power system analog bus pwm controller channels (lv) power fets (hv) power system digital bus hysteretic pwm hysteretic pwm hysteretic pwm hysteretic pwm gate driver (lv) gdrv gdrv gdrv gdrv sw regulator csa power peripherals chbond_bus dac dac dac dac dac dac dac ainx vref clock signals interupt bus csa csa csa [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 2 of 55 2. contents logic block diagrams ...................................................... 3 powerpsoc ? functional overview ................................. 9 power peripherals ............................................................ 9 hysteretic controllers ..................................................9 low side n-channel fets ........ ......................... .......10 external gate drivers ................................................10 dimming modulation schemes .. ......................... .......10 current sense amplifier ............................................10 voltage comparators ................................................11 reference dacs .......................................................11 built-in switching regulator ......................................11 analog multiplexer ............... ......................................11 digital multiplexer ................ ......................................12 function pins (fn0[0:3]) ..... ......................................12 psoc core ....................................................................... 13 digital system ...........................................................13 analog system ..........................................................13 analog multiplexer system ........................................14 additional system resources ...................................14 applications .................................................................... 15 powerpsoc device characteristi cs .............................. 16 getting started ................................................................ 17 application notes ......................................................17 development kits ......................................................17 training .....................................................................17 cypros consultants ..................................................17 technical support .....................................................17 development tools ........................................................ 17 psoc designer software subsyst ems .......... ............17 in-circuit emulator .....................................................18 designing with user modules ....................................... 18 pin information ............................................................... 19 cy8cled04d0x 56-pin part pinout (without ocd) ............................................................19 cy8cled04g01 56-pin part pinout (without ocd) ............................................................20 cy8cled04docd1 56-pin part pinout (with ocd) .................................................................21 cy8cled03d0x 56-pin part pinout (without ocd) ............................................................22 cy8cled03g01 56-pin part pinout (without ocd) ............................................................23 cy8cled02d01 56-pin part pinout (without ocd) ............................................................24 cy8cled01d01 56-pin part pinout (without ocd) ............................................................25 register general conventions ...................................... 26 abbreviations used ...................................................26 register naming conventions ...................................26 register mapping tables ..........................................26 register map bank 0 table .......................................26 register map bank 1 table: user space ..................27 electrical specifications ................................................ 29 absolute maximum ratings ... ....................................29 operating temperature .............................................30 electrical characteristics ............................................... 30 system level .............................................................30 chip level .................................................................30 power peripheral low side n-channel fet .........................................................32 power peripheral external power fet driver .................................................................33 power peripheral hysteretic controller .....................33 power peripheral comparator ...................................34 power peripheral current s ense amplifier ................35 power peripheral pwm/prism/dmm specification table ....................................................36 power peripheral reference dac specification ..............................................................37 power peripheral built-in switching regulator .............. .......................................... ...........37 general purpose i/o / function pin i/o .....................40 psoc core operational amplifier specifications ............................................................41 psoc core low power comparator .........................42 psoc core analog output buff er ..............................43 psoc core analog reference ..................................44 psoc core analog block ...... ....................................44 psoc core por and lvd ........................................45 psoc core programming specif ications ..................45 psoc core digital block specif ications ....................46 psoc core i2c specifications ..................................47 ordering information ...................................................... 48 ordering code definitions ..... .................................... 48 packaging information ................................................... 49 packaging dimensions ..............................................49 ther mal impedance ..................................................49 solder reflow peak temperat ure .............................49 acronyms ........................................................................ 50 document conventions ................................................. 50 units of measure .......................................................50 document history page ................................................. 52 sales, solutions, and legal information ...................... 53 worldwide sales and design s upport ......... ..............53 products ....................................................................53 psoc solutions .........................................................53 [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 3 of 55 3. logic block diagrams figure 3-1. cy8cled04d0x logic block diagram 4 channel pwm/ prism/dmm analog mux from analog mux comp 8 dac8 comp 9 comp 10 comp 11 comp 12 comp 13 auxiliary power regulator dac0 csp0 sw0 gd 0 hysteretic mode controller 0 pgnd0 csn0 dac1 csa0 dac2 csp1 sw1 gd 1 hysteretic mode controller 1 pgnd1 csn1 dac3 csa1 dac4 csp2 sw2 gd 2 hysteretic mode controller 2 pgnd2 csn2 dac5 csa2 dac6 csp3 sw3 gd 3 hysteretic mode controller 3 pgnd3 csn3 dac7 csa3 dac9 dac10 dac11 dac12 dac13 6 sregsw sreghvin gate drive 0 gate drive 1 gate drive 2 gate drive 3 external gate drive 0 external gate drive 1 external gate drive 2 external gate drive 3 power peripherals digital mux power peripherals analog mux digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. analog block array internal voltage ref. por and lvd system resets 2 macs decimator type 2 i2c s y s t e m b u s analog input muxing 4 4 p2[2] p0[3,4,5,7] p1[0,1,4,5,7] port 2 port 0 port 1 fn0 ainx sregcsn sregcsp sregfb sregcomp fn0[0:3] [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 4 of 55 figure 3-2. cy8cled04g01 logic block diagram 4 channel pwm/ prism/dmm analog mux from analog mux comp 8 dac8 comp 9 comp 10 comp 11 comp 12 comp 13 auxiliary power regulator dac0 csp0 gd 0 hysteretic mode controller 0 csn0 dac1 csa0 dac2 csp1 gd 1 hysteretic mode controller 1 csn1 dac3 csa1 dac4 csp2 gd 2 hysteretic mode controller 2 csn2 dac5 csa2 dac6 csp3 hysteretic mode controller 3 csn3 dac7 fn0[0:3] csa3 dac9 dac10 dac11 dac12 dac13 6 sregsw sreghvin external gate drive 0 external gate drive 1 external gate drive 2 external gate drive 3 power peripherals digital mux power peripherals analog mux digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. analog block array internal voltage ref. por and lvd system resets 2 macs decimator type 2 i2c s y s t e m b u s analog input muxing 4 4 p2[2] p0[3,4,5,7] p1[0,1,4,5,7] port 2 port 0 port 1 fn0 ainx sregcsn sregcsp sregfb sregcomp gd 3 [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 5 of 55 figure 3-3. cy8cled03d0x logic block diagram 3 channel pwm/ prism/dmm analog mux from analog mux comp 8 dac8 comp 9 comp 10 comp 11 comp 12 comp 13 auxiliary power regulator dac0 csp0 sw0 gd 0 hysteretic mode controller 0 pgnd0 csn0 dac1 csa0 dac2 csp1 sw1 gd 1 hysteretic mode controller 1 pgnd1 csn1 dac3 csa1 dac4 csp2 sw2 gd 2 hysteretic mode controller 2 pgnd2 csn2 dac5 csa2 fn0[0:3] dac9 dac10 dac11 dac12 dac13 6 sregsw sreghvin gate drive 0 gate drive 1 gate drive 2 external gate drive 0 external gate drive 1 external gate drive 2 power peripherals digital mux power peripherals analog mux digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. analog block array internal voltage ref. por and lvd system resets 2 macs decimator type 2 i2c s y s t e m b u s analog input muxing 4 4 p2[2] p0[3,4,5,7] p1[0,1,4,5,7] port 2 port 0 port 1 fn0 ainx sregcsn sregcsp sregfb sregcomp [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 6 of 55 figure 3-4. cy8cled03g01 logic block diagram 3 channel pwm/ prism/dmm analog mux from analog mux comp 8 dac8 comp 9 comp 10 comp 11 comp 12 comp 13 auxiliary power regulator dac0 csp0 gd 0 hysteretic mode controller 0 csn0 dac1 csa0 dac2 csp1 gd 1 hysteretic mode controller 1 csn1 dac3 csa1 dac4 csp2 gd 2 hysteretic mode controller 2 csn2 dac5 csa2 fn0[0:3] dac9 dac10 dac11 dac12 dac13 6 sregsw sreghvin external gate drive 0 external gate drive 1 external gate drive 2 power peripherals digital mux power peripherals analog mux digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. analog block array internal voltage ref. por and lvd system resets 2 macs decimator type 2 i2c s y s t e m b u s analog input muxing 4 4 p2[2] p0[3,4,5,7] p1[0,1,4,5,7] port 2 port 0 port 1 fn0 ainx sregcsn sregcsp sregfb sregcomp [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 7 of 55 figure 3-5. cy8cled02d01 logic block diagram 2 channel pwm/ prism/dmm analog mux from analog mux comp 8 dac8 comp 9 comp 10 comp 11 comp 12 comp 13 auxiliary power regulator dac0 csp0 sw0 gd 0 hysteretic mode controller 0 pgnd0 csn0 dac1 csa0 dac2 csp1 sw1 gd 1 hysteretic mode controller 1 pgnd1 csn1 dac3 csa1 fn0[0:3] dac9 dac10 dac11 dac12 dac13 6 sregsw sreghvin gate drive 0 gate drive 1 external gate drive 0 external gate drive 1 power peripherals digital mux power peripherals analog mux digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. analog block array internal voltage ref. por and lvd system resets 2 macs decimator type 2 i2c s y s t e m b u s analog input muxing 4 4 p2[2] p0[3,4,5,7] p1[0,1,4,5,7] port 2 port 0 port 1 fn0 ainx sregcsn sregcsp sregfb sregcomp [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 8 of 55 figure 3-6. cy8cled01d01 logic block diagram 1 channel pwm/ prism/dmm analog mux from analog mux comp 8 dac8 comp 9 comp 10 comp 11 comp 12 comp 13 auxiliary power regulator dac0 csp0 sw0 gd 0 hysteretic mode controller 0 pgnd0 csn0 dac1 csa0 fn0[0:3] dac9 dac10 dac11 dac12 dac13 6 sregsw sreghvin gate drive 0 external gate drive 0 power peripherals digital mux power peripherals analog mux digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. analog block array internal voltage ref. por and lvd system resets 2 macs decimator type 2 i2c s y s t e m b u s analog input muxing 4 4 p2[2] p0[3,4,5,7] p1[0,1,4,5,7] port 2 port 0 port 1 fn0 ainx sregcsn sregcsp sregfb sregcomp [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 9 of 55 4. powerpsoc ? functional overview the powerpsoc family incorporates programmable system-on-chip technology with the best in class power electronics controllers and switch ing devices to create easy to use power-system-on-chip soluti ons for lighting applications. all powerpsoc family devices are designed to replace traditional mcus, system ics, and the numerous discrete components that surround them. powerpsoc devices feature high performance power electronics including 1 ampere 2 mhz power fets, hysteretic controllers, current sense amplifiers, and prism/pwm modulators to create a complete power electronics solution for led power management. configurable power, analog, digital, and interconnect circuitry enables a high level of integration in a host of industrial, commercial, and consumer led lighting applications. this architecture integrates programmable analog and digital blocks to enable you to cr eate customized peripheral configurations that match the requirements of each individual application. additionally, the device includes a 24 mhz cpu, flash program memory, sram data memory, and configurable i/o in a range of convenient pinouts and packages. the powerpsoc architecture, as illustrated in the block diagrams, comprises five main areas: psoc core, digital system, analog system, system resources, and power peripherals, which include power fets, hysteretic controllers, current sense amplifiers, and prism/pwm modulators. configurable global busing combines all the device resources into a complete custom system. the powerpsoc fa mily of devices have 10-port i/os that connect to the global digital and analog interconnects, providing access to eight digital blocks and six analog blocks. 5. power peripherals powerpsoc is designed to operate at voltages from 7 v to 32 v, drive up to 1 ampere of current using internal mosfet switches, and over 1 ampere with external mosfets. this family of devices (cy8cled 0xd/g0y) combines up to four independent channels of constant current drivers. these drivers feature hysteretic controll ers with the programmable system-on-chip (psoc) that contains an 8-bit microcontroller, configurable digital and analog peripherals, and embedded flash memory. the cy8cled0xd/g0y is the fi rst product in the powerpsoc family to integrate power peripher als to add further integration for your power electronics applications.the powerpsoc family of intelligent power controller ics are used in lighting applications that need traditional mcus and discrete power electronics support. the power peripherals of the cy8cled0xd/g0y include up to four 32 volt power mosfets with current ratings up to 1 ampere each. it also inte grates gate drivers that enable applications to drive external mosfets for higher current and voltage capabilities. the controller is a programmable threshold hysteretic controller , with user-selectable feedback paths that uses the ic in current mode floating load buck, floating load buck-boost, and boost configurations. 5.1 hysteretic controllers the powerpsoc contains four h ysteretic controllers. there is one hysteretic controller for each channel of the device. the hysteretic controllers prov ide cycle by cycle switch control with fast transient response, which simplifies system design by requiring no external compensation. the hysteretic controllers include the following key features: four independent channels dac configurable thresholds wide switching frequency range from 20 khz to 2 mhz programmable minimum on and off time floating load buck, floating load buck-boost and boost topology controller the reference inputs (ref_a and ref_b in figure 5-1. ) of the hysteretic controller are provided by the reference dacs as illustrated in the top le vel block diagram (see figure 3-1. on page 3). the hysteretic control function output is generated by comparing the feedback value to two thre sholds. going below the lower threshold turns the switch on and exceeding the upper threshold turns the switch off as shown in figure 5-1. the output current waveforms are shown in figure 5-2. the hysteretic controller also controls the minimum on-time and off-time. this circuit prevents oscillation at very high frequencies; which can be very destruct ive to output switches. the output to the gate drivers is gated by the trip, dim and enable signals. the enable signal is a direct result of the enable bit in the control register fo r the hysteretic controller. the trip signal can be any digital signal that follows ttl logic (logic high and logic low). it is an active high input. the dim modulation signal is the output of the dedicated modulators that are present in the power peripherals, or any other digital modulation signal. figure 5-1. generating hysteretic control function output ref_b ref_a i fb lower limit comparator upper limit comparator min on timer min off timer s r q csa fn0[x] hyst out dim modulation enable trip function [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 10 of 55 figure 5-2. current waveforms the minimum on-time and off-time circuits in the powerpsoc prevent oscillations at very high frequencies, which can be very destructive to output switches. 5.2 low side n-channel fets the internal low side n-channel fets are designed to enhance system integration. the low si de n-channel fets include the following key features: drive capability up to 1 a switching times of 20 ns (rise and fall times) to ensure high efficiency (more than 90%) drain source voltage rating 32 v low r ds(on) to ensure high efficiency switching frequency up to 2 mhz 5.3 external gate drivers these gate drivers enable the use of external fets with higher current capabilities or lower r ds(on) . the external gate drivers directly drive mosfets that are used in switching applications. the gate driver provides mult iple programmable drive strength steps to enable improved emi management. the external gate drivers include the following key features: programmable drive strength options (25%, 50%, 75%, 100%) for emi management rise and fall times at 55 ns with 4 nf load 5.4 dimming modulation schemes there are three dimming modulation schemes available with the powerpsoc. the configurable modulation schemes are: precise intensity signal modulation (prism) delta sigma modulation mode (dmm) pulse width modulation (pwm) 5.4.1 prism mode configuration high resolution operation up to 16 bits dedicated prism module enables customers to use core psoc digital blocks for other needs clocking up to 48 mhz selectable output signal density reduced emi the prism mode compares the output of a pseudo-random counter with a signal density va lue. the comparator output asserts when the count value is less than or equal to the value in the signal density register. 5.4.2 dmm mode configuration high resolution operation up to 16 bits configurable output frequency and delta sigma modulator width to trade off repeat rates versus resolution dedicated dmm module enables customers to use psoc digital blocks for other uses clocking up to 48 mhz the dmm modulator consists of a 12-bit pwm block and a 4-bit delta sigma modulator (dsm) block. the width of the pwm, the width of the dmm, and the clo ck defines the output frequency. the duty cycle of the pwm output is dithered by using the dsm block which has a user-selectable resolution up to 4 bits. 5.4.3 pwm mode configuration high resolution operation up to 16 bits user programmable period from 1 to 65535 clocks dedicated pwm module enables customers to use core psoc digital blocks for other use interrupt on rising edge of the output or terminal count precise pwm phase control to manage system current edges phase synchronization among the four channels pwm output can be aligned to left, right, or center the pwm features a down counter and a pulse width register. a comparator output is asserted when the count value is less than or equal to the value in the pulse width register. 5.5 current sense amplifier the high side current sense amplifiers provide a differential sense capability to sense the voltage across current sense resistors in lighting systems. the current sense amplifier includes the following key features: operation with high common mode voltage to 32 v high common mode rejection ratio programmable bandwidth to opt imize system noise immunity an off-chip resistor r sense is used for high side current measurement as shown in figure 5-3. on page 11. the output of the current sense amplifier goes to the power peripherals analog multiplexer where, you select the hysteretic controller to which i led dim on off ref_b ref_a hyst out [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 11 of 55 the routing is done. table 5-1 illustrates example values of r sense for different currents. the method to calculate the r sense value for a desired average current is explained in the application note, floating load buck topology for hb-leds - an52699 figure 5-3. high side current measurement 5.6 voltage comparators there are six comparators that provide high speed comparator operation for over voltage, over current, and various other system event detections . for example, the comparators may be used for zero crossing detection for an ac input line or monitoring total dc bus current. programmable internal analog routing enables these comparators to monitor various analog signals. these comparators incl ude the following key features: high speed comparator operation: 100 ns response time programmable interrupt generation low input offset voltage and input bias currents six precision voltage comparators are available. the differential positive and negative inputs of t he comparators are routed from the analog multiplexer and the output goes to the digital multiplexer. a programmable inverter is used to select the output polarity. user-selectable hysteresis can be enabled or disabled to trade-off noise immunity versus comparator sensitivity. 5.7 reference dacs the reference dacs are used to generate set points for various analog modules such as hysteret ic controllers and comparators. the reference dacs include the following key features: 8-bit resolution guaranteed monotonic operation low gain errors 10 us settling time these dacs are available to provide programmable references for the various analog and comparator functions and are controlled by memory mapped registers. dac[0:7] are embedded in the hysteretic controllers and are required to set the upper and lower thresholds for channel 0 to 3. dac [8:13] are connected to the power peripherals analog multiplexer and provide programmable references to the comparator bank. these are used to set trip points which enable over voltage, over current, an d other system event detection. 5.8 built-in switching regulator the switching regulator is used to power the low voltage (5 v portion of the powerpsoc) from t he input line. this regulator is based upon a peak current control loop which can support up to 250 ma of output current. the current not being consumed by powerpsoc is used to power additional system per ipherals. the key features of the built-in switching regulator include: ability to self power device from input line small filter component sizes fast response to transients refer to table 16-20 for component values. the 'ref' signal that forms the re ference to the error amplifier is internally generated and there is no user control over it. figure 5-4. built-in switching regulator 5.9 analog multiplexer the powerpsoc family?s analog mux is designed to route signals from the csa output, function i/o pins and the dacs to comparator inputs and the current sense inputs of the hysteretic controllers. additionally, csa outp uts can be routed to the ainx block using this mux. for a full matrix representation of all possible routing using this mux, refer to the powerpsoc technical reference manual. the cpu configures the power peripherals analog multiplexer connections using memory mapped registers. the analog multiplexer includes the following key features: signal integrity for mi nimum signal corruption table 5-1. r sense values for di fferent currents max load current (ma) typical r sense (m ? ) 1000 100 750 130 500 200 350 300 csp0 csn0 csp3 csn3 cs3 cs0 . . . rsense3 rsense0 power peripheral analog mux error amplifier comparator ref c in sregfb sregsw current sense amplifier sreghvin v regin sregcsp sregcsn osc logic and gate drive sregcomp v regout = 5 v 1 d l r sense c comp r comp r fb1 r fb2 c 1 esr [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 12 of 55 5.10 digital multiplexer the powerpsoc family?s digital mux is a configurable switching matrix that connects the power peripheral digital resources. for a full matrix representation of all possible routing using this mux, refer to the powerpsoc technical reference manual. this power peripheral digital mu ltiplexer is independent of the main psoc digital buses or global interconnect of the psoc core. the digital multiplexer includes the following key features: connect signals to ensure needed flexibility 5.11 function pins (fn0[0:3]) the function i/o pins are a set of dedicated control pins used to perform system level functions with the power peripheral blocks of the powerpsoc. these pins are dynamically configurable, enabling them to perform a multitude of input and output functions. these i/os have direct access to the input and output of the voltage comparators, input of the hysteretic controller, and output of the digital pwm blocks for the device. the function i/o pins are register mapped. the microcontroller can control and read the state of these pins and the interrupt function. some of the key syst em benefits of t he function i/o are: enabling an external higher voltage current-sense amplifier as shown in figure 5-5. synchronizing dimming of multiple powerpsoc controllers as shown in figure 5-6. programmable fail-safe monitor and dedicated shutdown of hysteretic controller as shown in figure 5-7. along with the these functions, these i/os also provide interrupt functionality, enabling intelligent system responses to power control lighting system status. figure 5-5. external csa and fet application figure 5-6. powerpsoc in master/slave configuration figure 5-7. event detection fn0[0] fn0[3] fn0[2] fn0[1] hysteretic mode controller 0 external gate drive 0 dac0 dac1 hvdd gd 0 . . . vled > 32v external csa r sense + - external fet { . . . powerpsoc hysteretic mode controller 3 external gate drive 3 dac6 dac7 gd 3 powerpsoc (master) fn0[0] fn0[2] fn0[1] fn0[3] fn0[x] fn0[x] powerpsoc (slave 1) hysteretic controller dim powerpsoc (slave 3) hysteretic controller dim powerpsoc (slave 2) hysteretic controller dim powerpsoc (slave 0) hysteretic controller dim fn0[x] fn0[x] fn0[0] hysteretic mode controller 0 external gate drive 0 . . . event detect trip fn0[3] hysteretic mode controller 3 event detect trip . . . external gate drive 3 gd0 gd3 [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 13 of 55 6. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable general purpose i/o(gpio). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mi ps 8-bit harvard architecture microprocessor. the cpu uses an interrupt controller with up to 20 vectors to simplify programming of real time embedded events. the program execution is timed and protected using the included sleep and watchdog timers (wdt) time and protect program execution. memory encompasses 16 k of flash for program storage, 1k of sram for data stor age, and up to 2 k of eeprom emulated using the flash. program flash us es four protection levels on blocks of 64 bytes, a llowing customized software ip protection. the psoc device incorporates flex ible internal clock generators, including a 24 mhz internal main oscillator (imo) accurate to 4 percent over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and wdt. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the powerpsoc device. powerpsoc gpios provide connection to the cpu, digital, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, low level, and c hange from last read. 6.1 digital system the digital system contains eigh t digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. digital peripheral configurations include: dmx512 counters (8 to 32 bit) timers (8 to 32 bit) uart 8-bit with selectable parity spi master and slave i 2 c master, slave, and multi-master cyclical redundancy checker/generator (8 to 32 bit) irda pseudo random sequence generators (8 to 32 bit) note the dali interface is sup ported through the use of a combination of the above mentioned user modules. for more details on the exact configurati on and an example project, refer to the application note, implementing a dali receiver system using powerpsoc? - an52525 . the digital blocks can be connected to any gpio through a series of global buses that route any signal to any pin. the buses also allow signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. there are four digital blocks in each row. this allows optimum choice of system resources for your application. figure 6-1. digital system block diagram 6.2 analog system the analog system contains si x configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the more common powerpsoc analog functions (most available as user modules) are: analog-to-digital converters (up to 2, with 6 to 12-bit resolution, selectable as incremental, delta sigma, and sar) filters (2 and 4 pole band-pass, low-pass, and notch) amplifiers (up to 2, with selectable gain to 48x) instrumentation amplifiers (1 with selectable gain to 93x) comparators (up to 2, with 16 selectable thresholds) dacs (up to 2, with 6 to 9-bit resolution) multiplying dacs (up to 2, with 6 to 9-bit resolution) high current output drivers (two with 30 ma drive as a psoc core resource) 1.3 v reference (as a system resource) modulators correlators peak detectors many other topologies possible digital system d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] g o e[7:0] goo[7:0] global digital interconnect port 1 port 0 port 2 row input configuration row output configuration row 1 dbb10 dbb11 dcb12 dcb13 d 4 dbb00 4 to system bus [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 14 of 55 analog blocks are arranged in two columns of three blocks each, which includes one ct (continuous time) and two sc (switched capacitor) blocks, as shown in figure 6-2. on page 14 . figure 6-2. analog system block diagram 6.3 analog multiplexer system the analog mux bus connects to every gpio pin in ports 0 to 2. pins can be connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with comparators and analog-to-digital converters. it can be split into two sections for simultaneous dual-channel processing. an additional analog input multiplexer provides a second path to bring port 0 pins to the analog array. switch control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications such as touch sensing. other multiplexer applications include: track pad, finger sensing crosspoint connection between any i/o pin combinations like other psoc devices, powerpsoc has specific pins allocated to the reference capacitor (ref cap) and modulation resistor (mod resistor). these are indicated in the device pin outs (section 13). for more details on capacitive sensing, refer to the application notes an2394 - capsen se best practices, an2292 - capacitance sensing layout guidelines for psoc capsense and an47456 - design guide capsense buttons with csd. apart from these, there are a number of application notes on capacitive sensing on the cypress webbiest. the powerpsoc technical reference manual provides details on the analog system configuration that enables all i/os in the device to be capsense inputs. 6.4 additional system resources system resources provide additional capability useful in complete systems. additional re sources include a multiplier, decimator, low voltage detection, and power on reset. brief statements describing the merits of each resource follow. two multiply accumulates (macs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. a decimator provides a custom hardware filter for digital signal processing applications including creation of delta sigma adcs. low voltage detection (lvd) interrupts signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates t he need for a system supervisor. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and anal og systems. the designer can generate additional clocks using digital psoc blocks as clock dividers. the i 2 c module provides 100 and 400 khz communication over two wires. slave, master, and mu lti-master applications are supported. an internal 1.3 v reference provides an absolute reference for the analog system, including adcs and dacs. versatile analog mu ltiplexer system. acol1mux array array input configuration reference generators bandgap vdd vss agnd=vbg microcontroller interface (address bus, data bus, etc.) interface to digital system analog mux bus right acm0 acm1 ac1 p0[5] p0[7] p0[3] p1[5] p1[7] p1[1] p0[4] p1[4] p2[2] acol0mux aci0[1:0] aci1[1:0] analog mux bus left acb00 acb01 asc10 asd11 asd20 asc21 bcol1mux splitmux bit p1[0] ainx csa buffered output [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 15 of 55 7. applications the following figures show examples of applications in which the powerpsoc family of devices adds intelligent power control for power applications. figure 7-1. led lighting with rggb color mixing configured as floating load buck converter figure 7-2. led lighting with rgba color mixing driv ing external mosfets as floating load buck converter dual mode pwm 1 mod hvdd r sense dac1 dac0 dim hysteretic references hysteretic pwm hvdd r sense dac1 dac0 dim hysteretic references hvdd r sense dac1 dac0 dim hysteretic references hvdd r sense dac1 dac0 dim hysteretic references hysteretic pwm hysteretic pwm hysteretic pwm mod mod mod m8c core and irq configurable analog oscillator and power flash, ram, and rom i 2 c master and slave configurable digital blocks auxiliary power regulator hvdd r sense hvdd hvdd hvdd dual mode 1 dac0 dim references gate drive mod hysteretic pwm dual mode 1 dim references gate drive hysteretic pwm dual mode 1 dim references gate drive hysteretic pwm dual mode 1 dim references gate drive hysteretic pwm m8c core and irq configurable analog oscillator and power flash , ram , and rom i 2 c master and slave configurable digital blocks auxiliary power regulator r sense r sense r sense mod mod dac1 dac0 dac1 dac0 dac1 dac0 dac1 mod [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 16 of 55 figure 7-3. led lighting with a single channel boost driving three floating load buck channels 8. powerpsoc d evice characteristics there are two major groups of devices in the powerpsoc family. one group is a 4-channel 56-pin qfn and the other is a 3-channel 56-pin qfn. these are summarized in the following table. m8c core and irq configurable analog oscillator and power flash, ram, and rom i 2 c master and slave configurable digital blocks dac1 dac0 dim hysteretic references hysteretic pwm mod dac1 dac0 dim hysteretic references hysteretic pwm mod dac1 dac0 dim hysteretic references hysteretic pwm mod hvdd dac1 dac0 dim hysteretic references hysteretic pwm mod r sense auxiliary power regulator r sense r sense r sense table 8-1. powerpsoc device characteristics device group internal power fets external gate drivers digital i/o digital rows digital blocks analog inputs analog outputs analog col- umns analog blocks sram size flash size cy8cled04d01-56ltxi 4x1.0 a 4 14 2 8 14 2 2 6 1 k 16 k CY8CLED04D02-56ltxi 4x0.5 a 4 14 2 8 14 2 2 6 1 k 16 k cy8cled04g01-56ltxi 0 4 14 2 8 14 2 2 6 1 k 16 k cy8cled03d01-56ltxi 3x1.0 a 3 14 2 8 14 2 2 6 1 k 16 k cy8cled03d02-56ltxi 3x0.5 a 3 14 2 8 14 2 2 6 1 k 16 k cy8cled03g01-56ltxi 0 3 14 2 8 14 2 2 6 1 k 16 k cy8cled02d01-56ltxi 2x1.0 a 2 14 2 8 14 2 2 6 1 k 16 k cy8cled01d01-56ltxi 1x1.0 a 1 14 2 8 14 2 2 6 1 k 16 k cy8cled01d01-56ltxq 1x1.0 a 1 14 2 8 14 2 2 6 1 k 16 k [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 17 of 55 9. getting started the quickest way to understand the powerpsoc device is to read this datasheet and then use the psoc designer integrated development environment (ide). this datasheet is an overview of the powerpsoc integrated circuit and presents specific pin, register, and electrical specificat ions. for in depth information, along with detailed programming information, refer to the powerpsoc technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest powerpsoc device datasheets on the web at www.cypress.com . 9.1 application notes application notes are an excellent introduction to a wide variety of possible powerpsoc designs. layout guidelines, thermal management and firmware design guidelines are some of the topics covered. to view the powerpsoc application notes, go to htttp://www.cypre ss.com/powerpsoc and click on the application notes link. 9.2 development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for powerpsoc development. for more information on the kits or to purchase a kit from the cypress web site, go to htttp://www.cypre ss.com/powerpsoc and click on the development kits link. 9.3 training free powerpsoc technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of to pics and skill levels to assist you in your designs. 9.4 cypros consultants certified psoc consultants offer everything from technical assistance to completed powerpsoc designs. to contact or become a psoc consultant go to www.cypress.com/cypros . 9.5 technical support powerpsoc application engineers take pride in fast and accurate response. they can be reached with a 24-hour guaranteed response at http://www.cypre ss.com/support/ . if you cannot find an answer to your que stion, call technical support at 1-800-541-4736. 10. development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide runs on windows xp, windows vista, or windows 7. this system provides design database management by project, an integrated debugger with in -circuit emulator, in-system programming support, and built-in support for third-party assemblers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the powerpsoc family. 10.1 psoc designer software subsystems 10.1.1 chip-level view the chip-level view is a more traditional integrated development environment (ide) based on psoc designer. choose a base device to work with and then select different onboard analog and digital components called user modules that use the powerpsoc blocks. examples of user modules are current sense amplifiers, prism, pwm, dmm, floating lo ad buck, and boost. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configuration allows for changing configurations at run time. 10.1.2 code generation tools psoc designer supports multiple third party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to merge seamlessly with c code. link librari es automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the powerpsoc family of devices. the products allow you to create complete c programs for the powerpsoc family of devices. the optimizing c compilers provide all the features of c tailored to the powerpsoc architecture . they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 10.1.3 debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providi ng an internal view of the powerpsoc device. debugger commands allow the designer to read and program and read and write data memory, read and write i/o registers, read and write cp u registers, set and clear breakpoints, and provide program r un, halt, and st ep control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. 10.1.4 online help system the online help system displays on line, context-sensitive help for you. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials and links to fa qs and an online support forum to aid the designer in getting started. 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cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 18 of 55 10.2 in-circuit emulator a low cost, high functionality in -circuit emulator (ice) is available for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all powerpsoc devices. 11. designing with user modules the development process for the powerpsoc device differs from that of a traditional fixed function microprocessor. the configurable power, analog, and digital har dware blocks give the powerpsoc architecture a unique flexibility that pays dividends in managing specification chang e during development and by lowering inventory co sts. these configurable resources, called powerpsoc blocks, have the abilit y to implement a wide variety of user-selectable functions. the powerpsoc development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify and debug select components. in the chip-level view the components are called ?user modules?. user modules make selecting and implementing peripheral devices simple and come in power, analog, digital, and mixed signal varieties. the standard user module library contains over 50 common peripherals such as current sense amplifiers, prism, pwm, dmm, floating buck, boost, adcs, dacs, timers, counters, uarts, and other not so common peripherals such as dtmf generators and bi-quad analog filter sections. configure components. each of the components selected establishes the basic register settings that implement the selected function. they also provide parameters allowing precise configuration to your part icular application. for example, a pwm user module configures one or more digital psoc blocks, one for each 8 bits of resolution. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. the chip-level user modules are documented in datasheets that are viewed directly in psoc designer. these datasheets explain the internal operation of the component and provide performance specifications. each datasheet describes the use of each user module parameter and other information needed to successfully implement your design. organize and connect. signal chains can be built at the chip level by interconnecting user modules to each other and the i/o pins. in the chip-level view, perf orm the selection, configuration, and routing so that you have comp lete control over the use of all on-chip resources. generate, verify, and debug. when ready to test the hardware configuration or move on to developing code for the project, perform the ?generate applicat ion? step. this causes psoc designer to generate source code that automatical ly configures the device to your specification and provides the high level user module api functions. the chip-level designs generate software based on your design. the chip-level view provides application programming interfaces (apis) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. a complete code development env ironment allows development and customization of your applicat ions in c, assembly language, or both. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the ice where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single step, run-to-breakpoint and watch-variable features, the de bugger provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 19 of 55 12. pin information 12.1 cy8cled04d0x 56-pin part pinout (without ocd) the cy8cled04d01 and CY8CLED04D02 powerpsoc devices are ava ilable with the following pinout information. every port pin (labeled with a ?p? and ?fn0?) is capable of digital i/o. table 12-1. cy8cled04d0x 56-pin part pinout (qfn) pin no. type name description figure 12-1. cy8cled04d0x 56-pin powerpsoc device digital rows analog columns power peripherals 1 i/o i p1[0] gpio/i 2 c sda (secondary)/ issp sdata 2 i/o i p2[2] gpio/direct switch cap connection 3 i/o i/o p0[3] gpio/analog input (column 0)/ analog output (column 0) 4 i/o i/o p0[5] gpio/analog input (column 0)/ analog output (column 1)/ capsense ref cap 5 i/o i p0[7] gpio/analog input (column 0)/ capsense ref cap 6 i/o i p1[1] gpio/i 2 c scl (secondary)/issp sclk 7 i/o i p1[5] gpio/i 2 c sda (primary) 8 i/o i p1[7] gpio/i 2 c scl (primary) 9 v ss digital ground 10 nc no connect 11 nc no connect 12 nc no connect 13 nc no connect 14 i xres external reset 15 v dd digital power supply 16 v ss digital ground 17 av ss analog ground 18 av dd analog power supply 19 i csn2 current sense negative input - csa2 20 csp2 current sense positive input and power supply - csa2 21 csp3 current sense positive input and power supply - csa3 22 i csn3 current sense negative input 3 23 sregcomp voltage regulator error amp comp 24 i sregfb regulator voltage mode feedback node 25 i sregcsn current mode feedback negative 26 i sregcsp current mode feedback positive 27 o sregsw switch mode regulator out 28 sreghvin switch mode regulator in 29 gdv dd gate driver power supply pin no. type name description 30 gdv ss gate driver ground digital rows analog columns power peripherals 31 pgnd3 [1] power fet ground 3 44 gdv dd gate driver power supply 32 o gd3 external low side gate driver 3 45 i/o fn0[0] function i/o 33 sw3 power switch 3 46 i/o fn0[1] function i/o 34 pgnd2 [1] power fet ground 2 47 i/o fn0[2] function i/o 35 o gd2 external low side gate driver 2 48 i/o fn0[3] function i/o 36 sw2 power switch 2 49 i csn0 current sense negative input 0 37 sw1 power switch 1 50 csp0 current sense positive input and power supply - csa0 38 o gd1 external low side gate driver 1 51 csp1 current sense positive input and power supply - csa1 39 pgnd1 [1] power fet ground 1 52 i csn1 current sense negative input 1 40 sw0 power switch 0 53 i/o i p0[4] gpio/analog input (column 1) / bandgap output 41 o gd0 external low side gate driver 0 54 v dd digital power supply 42 pgnd0 [1] power fetground 0 55 v ss digital ground 43 gdv ss gate driver ground 56 i/o i p1[4] gpio / external clock input note 1. all pgndx pins must be connected to the ground plane on the pcb irrespective of whether the corresponding powerpsoc channel i s used or not. p1[0] p2[2] p0[3] p0[5] p0[7] p1[1] p1[5] p1[7] vss nc nc nc nc xres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd vss avss avdd csn2 csp2 csp3 csn3 sregcomp sregfb sregcsn sregcsp sreghvin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gdvss gdvdd fn0[0] fn0[1] fn0[2] fn0[3] csn0 csp0 csp1 csn1 p0[4] vdd vss p1[4] 43 44 45 46 47 48 49 50 51 52 53 54 55 56 pgnd0 gd0 sw0 pgnd1 gd1 sw1 sw2 gd2 pgnd2 sw3 gd3 pgnd3 gdvss gdvdd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 sregsw exposed pad qfn top view * connect exposed pad to pgndx [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 20 of 55 12.2 cy8cled04g01 56-pin part pinout (without ocd) the cy8cled04g01 powerpsoc device is available with the foll owing pinout information. every port pin (labeled with a ?p? and ?fn0?) is capable of digital i/o. table 12-2. cy8cled04g01 56-pin part pinout (qfn) pin no. type name description figure 12-2. cy8cled04g01 56-pin powerpsoc device digital rows analog columns power peripherals 1 i/o i p1[0] gpio/i 2 c sda (secondary)/ issp sdata 2 i/o i p2[2] gpio/direct switch cap connection 3 i/o i/o p0[3] gpio/analog input (column 0)/ analog output (column 0) 4 i/o i/o p0[5] gpio/analog input (column 0)/ analog output (column 1)/ capsense ref cap 5 i/o i p0[7] gpio/analog input (column 0)/ capsense ref cap 6 i/o i p1[1] gpio/i 2 c scl (secondary)/ issp sclk 7 i/o i p1[5] gpio/i 2 c sda (primary) 8 i/o i p1[7] gpio/i 2 c scl (primary) 9 v ss digital ground 10 nc no connect 11 nc no connect 12 nc no connect 13 nc no connect 14 i xres external reset 15 v dd digital power supply 16 v ss digital ground 17 av ss analog ground 18 av dd analog power supply 19 i csn2 current sense negative input 2 20 csp2 current sense positive input and power supply - csa2 21 csp3 current sense positive input and power supply - csa3 22 i csn3 current sense negative input 3 23 sregcomp voltage regulator error amp comp 24 i sregfb regulator voltage mode feedback node 25 i sregcsn current mode feedback negative 26 i sregcsp current mode feedback positive 27 o sregsw switch mode regulator out 28 sreghvin switch mode regulator in 29 gdv dd gate driver power supply pin no. type name description 30 gdv ss gate driver ground digital rows analog columns power peripherals 31 pgnd3 [3] power fet ground 3 44 gdv dd gate driver power supply 32 o gd3 external low side gate driver 3 45 i/o fn0[0] function i/o 33 dnc [2] do not connect 46 i/o fn0[1] function i/o 34 pgnd2 [3] power fet ground 2 47 i/o fn0[2] function i/o 35 o gd2 external low side gate driver 2 48 i/o fn0[3] function i/o 36 dnc [2] do not connect 49 i csn0 current sense negative input 0 37 dnc [2] do not connect 50 csp0 current sense positive input and power supply - csa0 38 o gd1 external low side gate driver 1 51 csp1 current sense positive input and power supply - csa1 39 pgnd1 [3] power fet ground 1 52 i csn1 current sense negative input 1 40 dnc [2] do not connect 53 i/o i p0[4] gpio/analog input (column 1) / bandgap output 41 o gd0 external low side gate driver 0 54 v dd digital power supply 42 pgnd0 [3] power fet ground 0 55 v ss digital ground 43 gdv ss gate driver ground 56 i/o i p1[4] gpio / external clock input notes 2. do not connect (dnc) pins must be left unconnected, or floatin g. connecting these pins to power or ground may cause improper operation or failure of the device. 3. all pgndx pins must be connected to the ground plane on the pcb irrespective of whether the corresponding powerpsoc channel i s used or not. qfn top view p1[0] p2[2] p0[3] p0[5] p0[7] p1[1] p1[5] p1[7] vss nc nc nc nc xres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d v v s s s 3 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gdvss gdvdd fn0[0] fn0[1] fn0[2] fn0[3] csn0 csp0 csp1 csn1 p0[4] vdd vss p1[4] 43 44 45 46 47 48 49 50 51 52 53 54 55 56 pgnd0 gd0 dnc pgnd1 gd1 dnc dnc gd2 pgnd2 dnc gd3 pgnd3 gdvss gdvdd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 exposed pad sreghvin sregsw sregcsp sregcsn sregfb sregcomp vd ass vs s add cn2 cp2 cp3 csn * connect exposed pad to pgndx [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 21 of 55 12.3 cy8cled04docd1 56-pin part pinout (with ocd) the cy8cled04docd1 powerpsoc device is available with the fo llowing pinout information. every port pin (labeled with a ?p? and ?fn0?) is capable of digital i/o. table 12-3. cy8cled04docd1 56-pin part pinout (qfn) pin no. type name description figure 12-3. cy8cled04docd1 56-pin powerpsoc device digital rows analog columns power peripherals 1 i/o i p1[0] gpio/i 2 c sda (secondary)/ issp sdata 2 i/o i p2[2] gpio/direct switch cap connection 3 i/o i/o p0[3] gpio/analog input (column 0)/ analog output (column 0) 4 i/o i/o p0[5] gpio/analog input (column 0)/ analog output (column 1) / capsense ref cap 5 i/o i p0[7] gpio/analog input (column 0)/ capsense ref cap 6 i/o i p1[1] gpio/i 2 c scl (secondary)/ issp sclk 7 i/o i p1[5] gpio/i 2 c sda (primary) 8 i/o i p1[7] gpio/i 2 c scl (primary) 9 v ss digital ground 10 i/o ocde on chip debugger port 11 i/o ocdo on chip debugger port 12 i/o cclk on chip debugger port 13 i/o hclk on chip debugger port 14 i xres external reset 15 v dd digital power supply 16 v ss digital ground 17 av ss analog ground 18 av dd analog power supply 19 i csn2 current sense negative input 2 20 csp2 current sense positive input and power supply - csa2 21 csp3 current sense positive input and power supply - csa3 22 i csn3 current sense negative input 3 23 sregcomp voltage regulator error amp comp 24 i sregfb regulator voltage mode feedback node 25 i sregcsn current mode feedback negative 26 i sregcsp current mode feedback positive 27 o sregsw switch mode regulator out 28 sreghvin switch mode regulator in 29 gdv dd gate driver power supply pin no. type name description 30 gdv ss gate driver ground digital rows analog columns power peripherals 31 pgnd3 [4] power fet ground 3 44 gdv dd gate driver power supply 32 o gd3 external low side gate driver 3 45 i/o fn0[0] function i/o 33 sw3 power switch 3 46 i/o fn0[1] function i/o 34 pgnd2 [4] power fet ground 2 47 i/o fn0[2] function i/o 35 o gd2 external low side gate driver 2 48 i/o fn0[3] function i/o 36 sw2 power switch 2 49 i csn0 current sense negative input 0 37 sw1 power switch 1 50 csp0 current sense positive input and power supply - csa0 38 o gd1 external low side gate driver 1 51 csp1 current sense positive input and power supply - csa1 39 pgnd1 [4] power fet ground 1 52 i csn1 current sense negative input 1 40 sw0 power switch 0 53 i/o i p0[4] gpio/analog input (column 1) / bandgap output 41 o gd0 external low side gate driver 0 54 v dd digital power supply 42 pgnd0 [4] power fet ground 0 55 v ss digital ground 43 gdv ss gate driver ground 56 i/o i p1[4] gpio / external clock input note 4. all pgndx pins must be connected to the ground plane on the pcb irrespective of whether the corresponding powerpsoc channel i s used or not. qfn top view p1[0] p2[2] p0[3] p0[5] p0[7] p1[1] p1[5] p1[7] vss ocde ocdo cclk hclk xres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd vss avss avdd csn2 csp2 csp3 csn3 sregcomp sregfb sregcsn sregcsp sreghvin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gdvss gdvdd fn0[0] fn0[1] fn0[2] fn0[3] csn0 csp0 csp1 csn1 p0[4] vdd vss p1[4] 43 44 45 46 47 48 49 50 51 52 53 54 55 56 pgnd0 gd0 sw0 pgnd1 gd1 sw1 sw2 gd2 pgnd2 sw3 gd3 pgnd3 gdvss gdvdd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 sregsw exposed pad * connect exposed pad to pgndx [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 22 of 55 12.4 cy8cled03d0x 56-pin part pinout (without ocd) the cy8cled03d01 and cy8cled03d02 powerp soc devices are available with the follo wing pinout information. every port pin (labeled with a ?p? and ?fn0?) is capable of digital i/o. table 12-4. cy8cled03d0x 56-pin part pinout (qfn) pin no. type name description figure 12-4. cy8cled03d0x 56-pin powerpsoc device digital rows analog columns power peripherals 1 i/o i p1[0] gpio/i 2 c sda (secondary)/ issp sdata 2 i/o i p2[2] gpio/direct switch cap connection 3 i/o i/o p0[3] gpio/analog input (column 0)/ analog output (column 0) 4 i/o i/o p0[5] gpio/analog input (column 0)/ analog output (column 1)/ capsense ref cap 5 i/o i p0[7] gpio/analog input (column 0)/ capsense ref cap 6 i/o i p1[1] gpio/i 2 c scl (secondary)/ issp sclk 7 i/o i p1[5] gpio/i 2 c sda (primary) 8 i/o i p1[7] gpio/i 2 c scl (primary) 9 v ss digital ground 10 nc no connect 11 nc no connect 12 nc no connect 13 nc no connect 14 i xres external reset 15 v dd digital power supply 16 v ss digital ground 17 av ss analog ground 18 av dd analog power supply 19 i csn2 current sense negative input - csa2 20 csp2 current sense positive input and power supply - csa2 21 dnc [5] do not connect 22 dnc [5] do not connect 23 sregcomp voltage regulator error amp comp 24 i sregfb regulator voltage mode feedback node 25 i sregcsn current mode feedback negative 26 i sregcsp current mode feedback positive 27 o sregsw switch mode regulator out 28 sreghvin switch mode regulator in 29 gdv dd gate driver power supply pin no. type name description 30 gdv ss gate driver ground digital rows analog columns power peripherals 31 pgnd3 [6] power fet ground 3 44 gdv dd gate driver power supply 32 dnc [5] do not connect 45 i/o fn0[0] function i/o 33 dnc [5] do not connect 46 i/o fn0[1] function i/o 34 pgnd2 [6] power fet ground 2 47 i/o fn0[2] function i/o 35 o gd2 external low side gate driver 2 48 i/o fn0[3] function i/o 36 sw2 power switch 2 49 i csn0 current sense negative input 0 37 sw1 power switch 1 50 csp0 current sense positive input and power supply - csa0 38 o gd1 external low side gate driver 1 51 csp1 current sense positive input and power supply - csa1 39 pgnd1 [6] power fet ground 1 52 i csn1 current sense negative input 1 40 sw0 power switch 0 53 i/o i p0[4] gpio/analog input (column 1) / bandgap output 41 o gd0 external low side gate driver 0 54 v dd digital power supply 42 pgnd0 [6] power fetground 0 55 v ss digital ground 43 gdv ss gate driver ground 56 i/o i p1[4] gpio / external clock input notes 5. do not connect (dnc) pins must be left unconnected, or floatin g. connecting these pins to power or ground may cause improper operation or failure of the device. 6. all pgndx pins must be connected to the ground plane on the pcb irrespective of whether the corresponding powerpsoc channel i s used or not. p1[0] p2[2] p0[3] p0[5] p0[7] p1[1] p1[5] p1[7] vss nc nc nc nc xres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd vss avss avdd csn2 csp2 dnc dnc sregcomp sregfb sregcsn sregcsp sreghvin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gdvss gdvdd fn0[0] fn0[1] fn0[2] fn0[3] csn0 csp0 csp1 csn1 p0[4] vdd vss p1[4] 43 44 45 46 47 48 49 50 51 52 53 54 55 56 pgnd0 gd0 sw0 pgnd1 gd1 sw1 sw2 gd2 pgnd2 dnc dnc pgnd3 gdvss gdvdd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 sregsw exposed pad qfn top view * connect exposed pad to pgndx [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 23 of 55 12.5 cy8cled03g01 56-pin part pinout (without ocd) the cy8cled03g01 powerpsoc device is avai lable with the following pinout information. every port pin (labeled with a ?p? and ?fn0?) is capable of digital i/o. table 12-5. cy8cled03g01 56-pin part pinout (qfn) notes 7. do not connect (dnc) pins must be left unconnected, or floatin g. connecting these pins to power or ground may cause improper operation or failure of the device. 8. all pgndx pins must be connected to the ground plane on the pcb irrespective of whether the corresponding powerpsoc channel i s used or not. pin no. type name description figure 12-5. cy8cled03g01 56-pin powerpsoc device digital rows analog columns power peripherals 1 i/o i p1[0] gpio/i 2 c sda (secondary)/ issp sdata 2 i/o i p2[2] gpio/direct switch cap connection 3 i/o i/o p0[3] gpio/analog input (column 0)/ analog output (column 0) 4 i/o i/o p0[5] gpio/analog input (column 0)/ analog output (column 1)/ capsense ref cap 5 i/o i p0[7] gpio/analog input (column 0)/ capsense ref cap 6 i/o i p1[1] gpio/i 2 c scl (secondary)/ issp sclk 7 i/o i p1[5] gpio/i 2 c sda (primary) 8 i/o i p1[7] gpio/i 2 c scl (primary) 9 v ss digital ground 10 nc no connect 11 nc no connect 12 nc no connect 13 nc no connect 14 i xres external reset 15 v dd digital power supply 16 v ss digital ground 17 av ss analog ground 18 av dd analog power supply 19 i csn2 current sense negative input 2 20 csp2 current sense positive input and power supply - csa2 21 dnc [7] do not connect 22 dnc [7] do not connect 23 sregcomp voltage regulator error amp comp 24 i sregfb regulator voltage mode feedback node 25 i sregcsn current mode feedback negative 26 i sregcsp current mode feedback positive 27 o sregsw switch mode regulator out 28 sreghvin switch mode regulator in 29 gdv dd gate driver power supply pin no. type name description 30 gdv ss gate driver ground digital rows analog columns power peripherals 31 pgnd3 [8] power fet ground 3 44 gdv dd gate driver power supply 32 dnc [7] do not connect 45 i/o fn0[0] function i/o 33 dnc [7] do not connect 46 i/o fn0[1] function i/o 34 pgnd2 [8] power fet ground 2 47 i/o fn0[2] function i/o 35 o gd2 external low side gate driver 2 48 i/o fn0[3] function i/o 36 dnc [7] do not connect 49 i csn0 current sense negative input 0 37 dnc [7] do not connect 50 csp0 current sense positive input and power supply - csa0 38 o gd1 external low side gate driver 1 51 csp1 current sense positive input and power supply - csa1 39 pgnd1 [8] power fet ground 1 52 i csn1 current sense negative input 1 40 dnc [7] do not connect 53 i/o i p0[4] gpio/analog input (column 1) / bandgap output 41 o gd0 external low side gate driver 0 54 v dd digital power supply 42 pgnd0 [8] power fet ground 0 55 v ss digital ground 43 gdv ss gate driver ground 56 i/o i p1[4] gpio / external clock input * connect exposed pad to pgndx p1[0] p2[2] p0[3] p0[5] p0[7] p1[1] p1[5] p1[7] vss nc nc nc nc xres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd vss avss avdd csn2 csp2 dnc dnc sregcomp sregfb sregcsn sregcsp sreghvin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gdvss gdvdd fn0[0] fn0[1] fn0[2] fn0[3] csn0 csp0 csp1 csn1 p0[4] vdd vss p1[4] 43 44 45 46 47 48 49 50 51 52 53 54 55 56 pgnd0 gd0 dnc pgnd1 gd1 dnc dnc gd2 pgnd2 dnc dnc pgnd3 gdvss gdvdd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 sregsw exposed pad qfn top view [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 24 of 55 12.6 cy8cled02d01 56-pin part pinout (without ocd) the cy8cled02d01 powerpsoc devices are available with the follow ing pinout information. every port pin (labeled with a ?p? and ?fn0?) is capable of digital i/o. table 12-6. cy8cled02d01 56-pin part pinout (qfn) pin no. type name description figure 12-6. cy8cled02d01 56-pin powerpsoc device digital rows analog columns power peripherals 1 i/o i p1[0] gpio/i 2 c sda (secondary)/ issp sdata 2 i/o i p2[2] gpio/direct switch cap connection 3 i/o i/o p0[3] gpio/analog input (column 0)/ analog output (column 0) 4 i/o i/o p0[5] gpio/analog input (column 0)/ analog output (column 1)/ capsense ref cap 5 i/o i p0[7] gpio/analog input (column 0)/ capsense ref cap 6 i/o i p1[1] gpio/i 2 c sclk (secondary)/ issp sclk 7 i/o i p1[5] gpio/i 2 c sda (primary) 8 i/o i p1[7] gpio/i 2 c scl (primary) 9 v ss digital ground 10 nc no connect 11 nc no connect 12 nc no connect 13 nc no connect 14 i xres external reset 15 v dd digital power supply 16 v ss digital ground 17 av ss analog ground 18 av dd analog power supply 19 dnc [9] do not connect 20 dnc [9] do not connect 21 dnc [9] do not connect 22 dnc [9] do not connect 23 sregcomp voltage regulator error amp comp 24 i sregfb regulator voltage mode feedback node 25 i sregcsn current mode feedback negative 26 i sregcsp current mode feedback positive 27 o sregsw switch mode regulator out 28 sreghvin switch mode regulator in 29 gdv dd gate driver power supply pin no. type name description 30 gdv ss gate driver ground digital rows analog columns power peripherals 31 pgnd3 [10] power fet ground 3 44 gdv dd gate driver power supply 32 dnc [9] do not connect 45 i/o fn0[0] function i/o 33 dnc [9] do not connect 46 i/o fn0[1] function i/o 34 pgnd2 [10] power fet ground 2 47 i/o fn0[2] function i/o 35 dnc [9] do not connect 48 i/o fn0[3] function i/o 36 dnc [9] do not connect 49 i csn0 current sense negative input 0 37 sw1 power switch 1 50 csp0 current sense positive input and power supply - csa0 38 o gd1 external low side gate driver 1 51 csp1 current sense positive input and power supply - csa1 39 pgnd1 [10] power fet ground 1 52 i csn1 current sense negative input 1 40 sw0 power switch 0 53 i/o i p0[4] gpio/analog input (column 1) / bandgap output 41 o gd0 external low side gate driver 0 54 v dd digital power supply 42 pgnd0 [10] power fetground 0 55 v ss digital ground 43 gdv ss gate driver ground 56 i/o i p1[4] gpio / external clock input notes 9. do not connect (dnc) pins must be left unconnected, or floatin g. connecting these pins to power or ground may cause improper operation or failure of the device. 10. all pgndx pins must be connected to the ground plane on the pcb irrespective of whether the corresponding powerpsoc channel is used or not. p1[0] p2[2] p0[3] p0[5] p0[7] p1[1] p1[5] p1[7] vss nc nc nc nc xres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd vss avss avdd dnc dnc dnc dnc sregcomp sregfb sregcsn sregcsp sreghvin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gdvss gdvdd fn0[0] fn0[1] fn0[2] fn0[3] csn0 csp0 csp1 csn1 p0[4] vdd vss p1[4] 43 44 45 46 47 48 49 50 51 52 53 54 55 56 pgnd0 gd0 sw0 pgnd1 gd1 sw1 dnc dnc pgnd2 dnc dnc pgnd3 gdvss gdvdd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 sregsw exposed pad qfn top view * connect exposed pad to pgndx [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 25 of 55 12.7 cy8cled01d01 56-pin part pinout (without ocd) the cy8cled01d01 powerpsoc device is available with the following pinout information. every port pin (labeled with a ?p? and ?fn0?) is capable of digital i/o. table 12-7. cy8cled01d01 56-pin part pinout (qfn) notes 11. do not connect (dnc) pins must be left unconnected, or floatin g. connecting these pins to power or ground may cause improper operation or failure of the device. 12. all pgndx pins must be connected to the ground plane on the pcb irrespective of whether the corresponding powerpsoc channel is used or not. pin no. type name description figure 12-7. cy8cled01d01 56-pin powerpsoc device digital rows analog columns power peripherals 1 i/o i p1[0] gpio/i 2 c sda (secondary)/ issp sdata 2 i/o i p2[2] gpio/direct switch cap connection 3 i/o i/o p0[3] gpio/analog input (column 0)/ analog output (column 0) 4 i/o i/o p0[5] gpio/analog input (column 0)/ analog output (column 1)/ capsense ref cap 5 i/o i p0[7] gpio/analog input (column 0)/ capsense ref cap 6 i/o i p1[1] gpio/i 2 c sclk (secondary)/ issp sclk 7 i/o i p1[5] gpio/i 2 c sda (primary) 8 i/o i p1[7] gpio/i 2 c scl (primary) 9 v ss digital ground 10 nc no connect 11 nc no connect 12 nc no connect 13 nc no connect 14 i xres external reset 15 v dd digital power supply 16 v ss digital ground 17 av ss analog ground 18 av dd analog power supply 19 dnc [11] do not connect 20 dnc [11] do not connect 21 dnc [11] do not connect 22 dnc [11] do not connect 23 sregcomp voltage regulator error amp comp 24 i sregfb regulator voltage mode feedback node 25 i sregcsn current mode feedback negative 26 i sregcsp current mode feedback positive 27 o sregsw switch mode regulator out 28 sreghvin switch mode regulator in 29 gdv dd gate driver power supply pin no. type name description 30 gdv ss gate driver ground digital rows analog columns power peripherals 31 pgnd3 [12] power fet ground 3 44 gdv dd gate driver power supply 32 dnc [11] do not connect 45 i/o fn0[0] function i/o 33 dnc [11] do not connect 46 i/o fn0[1] function i/o 34 pgnd2 [12] power fet ground 2 47 i/o fn0[2] function i/o 35 dnc [11] do not connect 48 i/o fn0[3] function i/o 36 dnc [11] do not connect 49 i csn0 current sense negative input 0 37 dnc [11] do not connect 50 csp0 current sense positive input and power supply - csa0 38 dnc [11] do not connect 51 dnc [11] do not connect 39 pgnd1 [12] power fet ground 1 52 dnc [11] do not connect 40 sw0 power switch 0 53 i/o i p0[4] gpio/analog input (column 1) / bandgap output 41 o gd0 external low side gate driver 0 54 v dd digital power supply 42 pgnd0 [12] power fet ground 0 55 v ss digital ground 43 gdv ss gate driver ground 56 i/o i p1[4] gpio / external clock input * connect exposed pad to pgndx p1[0] p2[2] p0[3] p0[5] p0[7] p1[1] p1[5] p1[7] vss nc nc nc nc xres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd vss avss avdd dnc dnc dnc dnc sregcomp sregfb sregcsn sregcsp sreghvin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gdvss gdvdd fn0[0] fn0[1] fn0[2] fn0[3] csn0 csp0 dnc dnc p0[4] vdd vss p1[4] 43 44 45 46 47 48 49 50 51 52 53 54 55 56 pgnd0 gd0 sw0 pgnd1 dnc dnc dnc dnc pgnd2 dnc dnc pgnd3 gdvss gdvdd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 sregsw exposed pad qfn top view [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 26 of 55 13. register general conventions 13.1 abbreviations used the register conventions specific to this section are listed in table 13-1 . 13.2 register naming conventions the register naming convention specific to the psoc core section of powerpsoc blocks and their registers is: mn where m = row index, n = column index therefore, asd13cr3 is a register for an analog powerpsoc block in row 1 column 3. the register naming convention specific to the power peripheral section of powerpsoc blocks and their registers is: x where x = number of channel therefore, csa0_cr is a register for a power peripheral powerpsoc block in for current sense amplifier, channel 0. 13.3 register mapping tables the powerpsoc device has a total register address space of 512 bytes. the register space is also referred to as i/o space and is broken into two parts. the xio bit in the flag register (cpu_f) determines which bank you are currently in. when the xio bit is set, you are said to be in the ?extended? address space or the ?configuration? registers. more detailed description of the registers are found in the powerpsoc trm. the trm can be found at http://www.cypress. com/powerpsoc and clicking on the technical reference manual link. table 13-1. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 27 of 55 13.4 register map bank 0 table name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dpwm0pcf 40 rw asc10cr0 80 rw vdac0_cr c0 rw prt0ie 01 rw dpwm0pdh 41 rw asc10cr1 81 rw vdac0_dr0 c1 rw prt0gs 02 rw dpwm0pdl 42 rw asc10cr2 82 rw vdac0_dr1 c2 rw prt0dm2 03 rw dpwm0pwh 43 rw asc10cr3 83 rw c3 prt1dr 04 rw dpwm0pwl 44 rw asd11cr0 84 rw vdac1_cr c4 rw prt1ie 05 rw dpwm0pch 45 rw asd11cr1 85 rw vdac1_dr0 c5 rw prt1gs 06 rw dpwm0pcl 46 rw asd11cr2 86 rw vdac1_dr1 c6 rw prt1dm2 07 rw dpwm0gcfg 47 rw asd11cr3 87 rw c7 prt2dr 08 rw dpwm1pcf 48 rw 88 vdac2_cr c8 rw prt2ie 09 rw dpwm1pdh 49 rw 89 vdac2_dr0 c9 rw prt2gs 0a rw dpwm1pdl 4a rw 8a vdac2_dr1 ca rw prt2dm2 0b rw dpwm1pwh 4b rw 8b cb fn0dr 0c rw dpwm1pwl 4c rw 8c vdac3_cr cc rw fn0ie 0d rw dpwm1pch 4d rw 8d vdac3_dr0 cd rw fn0gs 0e rw dpwm1pcl 4e rw 8e vdac3_dr1 ce rw fn0dm2 0f rw dpwm1gcfg 4f rw 8f cf 10 dpwm2pcf 50 rw asd20cr0 90 rw cur_pp d0 rw 11 dpwm2pdh 51 rw asd20cr1 91 rw stk_pp d1 rw 12 dpwm2pdl 52 rw asd20cr2 92 rw d2 13 dpwm2pwh 53 rw asd20cr3 93 rw idx_pp d3 rw 14 dpwm2pwl 54 rw asc21cr0 94 rw mvr_pp d4 rw 15 dpwm2pch 55 rw asc21cr1 95 rw mvw_pp d5 rw 16 dpwm2pcl 56 rw asc21cr2 96 rw i2c_cfg d6 rw 17 dpwm2gcfg 57 rw asc21cr3 97 rw i2c_scr d7 # pdmux_s1 18 rw dpwm3pcf 58 rw 98 i2c_dr d8 rw pdmux_s2 19 rw dpwm3pdh 59 rw 99 i2c_mscr d9 # pdmux_s3 1a rw dpwm3pdl 5a rw 9a int_clr0 da rw pdmux_s4 1b rw dpwm3pwh 5b rw 9b int_clr1 db rw pdmux_s5 1c rw dpwm3pwl 5c rw vdac6_cr 9c rw int_clr2 dc rw pdmux_s6 1d rw dpwm3pch 5d rw vdac6_dr0 9d rw int_clr3 dd rw 1e dpwm3pcl 5e rw vdac6_dr1 9e rw int_msk3 de rw chbond_cr 1f rw dpwm3gcfg 5f rw 9f int_msk2 df rw dbb00dr0 20 # amx_in 60 rw vdac4_cr a0 rw int_msk0 e0 rw dbb00dr1 21 w amux_cfg 61 rw vdac4_dr0 a1 rw int_msk1 e1 rw dbb00dr2 22 rw 62 vdac4_dr1 a2 rw int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # vdac5_cr a4 rw dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # vdac5_dr0 a5 rw dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw vdac5_dr1 a6 rw dec_cr0 e6 rw dbb01cr0 27 # pamux_s1 67 rw a7 dec_cr1 e7 rw dcb02dr0 28 # pamux_s2 68 rw mul1_x a8 w mul0_x e8 w dcb02dr1 29 w pamux_s3 69 rw mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw pamux_s4 6a rw mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # dpwm0pcfg 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w dpwm1pcfg 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw dpwm2pcfg 7a rw rdi1is ba rw fa dcb12cr0 3b # dpwm3pcfg 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # dpwmintflg 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w dpwmintmsk 7d rw rdi1ro0 bd rw dac_d fd rw dcb13dr2 3e rw dpwmsync 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # 7f bf cpu_scr0 ff # [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 28 of 55 13.5 register map bank 1 table: user space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw csa0_cr 40 rw asc10cr0 80 rw cmpch0_cr c0 rw prt0dm1 01 rw 41 asc10cr1 81 rw cmpch2_cr c1 rw prt0ic0 02 rw 42 asc10cr2 82 rw cmpch4_cr c2 rw prt0ic1 03 rw 43 asc10cr3 83 rw cmpch6_cr c3 rw prt1dm0 04 rw csa1_cr 44 rw asd11cr0 84 rw cmpbnk8_cr c4 rw prt1dm1 05 rw 45 asd11cr1 85 rw cmpbnk9_cr c5 rw prt1ic0 06 rw 46 asd11cr2 86 rw cmpbnk10_cr c6 rw prt1ic1 07 rw 47 asd11cr3 87 rw cmpbnk11_cr c7 rw prt2dm0 08 rw csa2_cr 48 rw 88 cmpbnk12_cr c8 rw prt2dm1 09 rw 49 89 cmpbnk13_cr c9 rw prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb fn0dm0 0c rw csa3_cr 4c rw 8c cc fn0dm1 0d rw 4d 8d cd fn0ic0 0e rw 4e 8e ce fn0ic1 0f rw 4f 8f cf 10 50 asd20cr0 90 rw gdi_o_in d0 rw 11 51 asd20cr1 91 rw gdi_e_in d1 rw 12 52 asd20cr2 92 rw gdi_o_ou d2 rw 13 53 asd20cr3 93 rw gdi_e_ou d3 rw 14 54 asc21cr0 94 rw hysctlr0cr d4 rw 15 55 asc21cr1 95 rw hysctlr1cr d5 rw 16 56 asc21cr2 96 rw hysctlr2cr d6 rw 17 57 asc21cr3 97 rw hysctlr3cr d7 rw 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b db 1c 5c 9c sreg_tst dc rw 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 dec_cr2 e7 rw dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 rw dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 rw dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eb dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw amux_clk af rw ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb01in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb01ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw 78 rdi1ri b8 rw f8 dcb12in 39 rw gdrv0_cr 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw 7a rdi1is ba rw fa 3b gdrv1_cr 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw 7c rdi1lt1 bc rw fc dcb13in 3d rw gdrv2_cr 7d rw rdi1ro0 bd rw dac_cr fd rw dcb13ou 3e rw 7e rdi1ro1 be rw cpu_scr1 fe # 3f gdrv3_cr 7f rw bf cpu_scr0 ff # [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 29 of 55 14. electrical specifications this section presents the dc and ac electrical specific ations of the cy8cled04d0x, cy8cled04g01, cy8cled03d0x, cy8cled03g01, cy8cled02d01, and cy8cled01d01 of the power psoc device family. for the most up to date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypre ss.com/powerpsoc . specifications for industrial rated devices are valid for ?40 c ? t a ? 85 c, t j ? 115 c and for extended temperature rated devices for ?40 c ? t a ? 105 c, t j ? 125 c, except where noted. 14.1 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. not all user guidelines are production tested. table 14-1. absolu te maximum ratings symbol description min typ max units notes t stg storage temperature ?55 ? +115 c higher storage temperatures reduces data retention time. recommended storage temper- ature is 0 c to 50 c. t a ambient temperature with power applied ?40 -40 ? ? +85 +105 c c t j ?? 115 c (industrial rated) t j ?? 125 c (extended temper- ature rated) v dd , av dd , gdv dd supply voltage on v dd , av dd , and gdv dd ?0.5 ? +6.0 v relative to v ss , av ss , and gdv ss respectively v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v applies only to gpio and fn0 pins v io2 dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v v fet maximum voltage from power switch (swx) to power fet ground (pgndx) ? ? 36 [13] v pgndx is connected to gdv ss v regin maximum voltage on sreghvin pin relative to v ss ? ? 36 [13] v v csp, v csn maximum voltage applied to csa pins relative to v ss ?0.5 ? 36 [13] v v sense maximum input differential voltage across csa input ?1.0 ? 1.0 v i maio maximum current into any port pin configured as analog driver ?50 ? +50 ma i mio maximum current into any port and function pin ?25 ? +50 ma lu latch up current 200 ? ? ma jesd78a conformal esd electrostatic discharge voltage 2000 ? ? v human body model esd. sr regin ramp rate for the sreghvin pin ? ? 32 v/ ? s sr csp ramp rate for the cspx pins ? ? 3.2 v/ ? s sr h v dd-flb high voltage supply ramp rate for floating load buck configuration ? ? 15 v/ms for other topologies, to enable operation with faster ramp rates, or if the led string voltage is < 6.5 v, see the powerpsoc technical reference manual . srv dd-ext external v dd supply ramp rate (v dd , av dd , and gdv dd pins) ? ? 0.2 v/ ? s applies only when powered by a source other than the built-in switching regulator note 13. stresses beyond the ?absolute maximum ratings? on page 29 may cause permanent damage to the device. you must ensure that the absolute maximum ratings are never exceeded. functional operation is not implied under any conditions beyond the ?electrical characteristics? on page 30 onwards. extended exposure to ?absolute maximum ratings? on page 29 may affect reliability of the device. [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 30 of 55 14.2 operating temperature 15. electrical characteristics 15.1 system level the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. 15.2 chip level the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. note see the powerpsoc technical reference manual for more information on the dpwmxpcf register symbol description min typ max units notes t a ambient temperature ?40 ?40 ? ? +85 +105 c c t j ?? 115 c (industrial rated) t j ?? 125 c (extended temperature rated) t j junction temperature ?40 ?40 ? ? +115 +125 c c industrial rated extended temperature rated table 15-1. system level operating specifications symbol description min typ max units notes f sw circuit switching frequency range for hysteretic control loop 0.02 ? 2 mhz t d,max maximum delay time from csa input to fet state change ? ? ? ? 100 115 ns ns hv dd = 24 v, i d = 1 a, f sw = 2 mhz (industrial rated) hv dd = 24 v, i d = 1 a, f sw = 2 mhz (extended temperature rated) d output duty cycle for hysteretic controllers 5 ? 95 % f sw < 0.25 mhz e power converter efficiency 90 95 ? % hv dd = 24 v, i d = 1 a, f sw = 2 mhz table 15-2. chip level dc specifications symbol description min typ max units notes v dd , av dd, gdv dd digital, analog, and gate driver supply voltage range 4.75 ? 5.25 v all should be powered from the same source. hv dd power converter high voltage supply range 7 ? 32 v hv pins voltage range for the cspx and sreghvin pins 7 ? 32 v not all pins need to be at the same voltage level. iv dd supply current (v dd pins), imo = 24 mhz ? 16 50 ma conditions are v dd = 5 v, t j = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. i a v dd supply current (av dd pin) ? ? 25 ma conditions are v dd = 5 v, t j = 25 c, [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 31 of 55 figure 15-1. 24 mhz period jitter (imo) ti ming diagram i gd v dd supply current per channel (gdv dd pins) ? ? ? ? 25 100 ma ma internal power fet at 2 mhz external gate driver at 1 mhz, c l = 4 nf at v dd = 5 v i sb sleep (mode) current with por, lvd, sleep timer, and wdt. ? ? 18 30 25 550 ? a ? a t j ? 25 c, built-in switching regulator disabled, dpwmxpcf = 0, power peripherals disabled, analog power = off t j ? 115 c (industrial rated) and t j ? 125 c (extended temperature rated), built-in switching regulator disabled, dpwmxpcf = 0, power peripherals disabled, analog power = off table 15-3. chip level ac specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.04 24 24.96 mhz f cpu1 cpu frequency 0.093 24 24.96 mhz f blk digital psoc block frequency 0 48 49.92 [14 ] mhz refer to ?psoc core digital block specifications? on page 48. f 32k1 internal low-speed oscillator frequency 15 32 64 khz f 32k_u internal low speed oscillator (ilo) untrimmed frequency 5 ? ? khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the powerpsoc technical reference manual for details on timing this. dc ilo internal low speed oscillator duty cycle 20 50 80 % jitter 32k 32 khz period jitter ? 100 ? ns jitter 24m1 24 mhz period jitter (imo) peak-to-peak ? 600 ? ps t powerup time from end of por to cpu executing code ? 30 100 ms power up from 0 v. see the system resets section of the powerpsoc technical reference manual. table 15-2. chip level dc specifications symbol description min typ max units notes note 14. see the individual user module datasheets for information on maximum frequencies for user modules. [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 32 of 55 15.3 power peripheral low side n-channel fet the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. figure 15-2. low side n-channel fet test circuit for i dss, t r, and t f table 15-4. low side n-channel fet dc specifications symbol description min typ max units notes v ds operating drain to source voltage ? ? 32 v v ds,inst instantaneous drain source voltage ? ? 36 v i d average drain current ? ? ? ? 1 0.5 a a cy8cled04/3/2/1d01 devices cy8cled04/3d02 devices i dmax maximum instantaneous repetitive pulsed current ? ? ? ? 3 1.5 a a less than 33% duty cycle for an average current of 1 a, f sw = 0.1 mhz. cy8cled04/3/2/1d01 devices less than 33% duty cycle for an average current of 0.5 a, f sw = 0.1 mhz. cy8cled04/3d02 devices r ds(on) drain to source on resistance ? ? ? ? 0.5 1 ? ? i d = 1 a, gdv dd = 5 v, t j = 25 c cy8cled04/3/2/1d01 devices i d = 0.5 a, gdv dd = 5 v, t j = 25 c cy8cled04/3d02 devices i dss switching node to pgnd leakage ? ? ? ? 10 250 ? a ? a t j = 25 c t j ? 115 c (industrial rated) and t j ? 125 c (extended temperature rated) i sfet supply current per channel - fet (internal gate driver) ? ? 6.25 ma f sw = 2 mhz table 15-5. low side n-channel fet ac specifications symbol description min typ max units notes t r rise time ? ? 20 ns i d = 1 a, r d = 32 ? t f fall time ? ? 20 ns i d = 1 a, r d = 32 ? r g r d i d v g v inpu t [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 33 of 55 15.4 power peripheral exte rnal power fet driver the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. 15.5 power peripheral hy steretic controller the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. table 15-6. power fet driver dc specifications symbol description min typ max units notes v ohn n-channel fet driver output voltage -drive high v dd ? 0.45 v dd ? 0.10 ? ? ? ? v v i oh = 100 ma i oh = 10 ma v oln n-channel fet driver output voltage -drive low ? ? ? ? 0.45 0.1 v v i ol = 100 ma i ol = 10 ma i sfetdrv supply current per channel - external fet driver ? ? 25 ma c l = 4 nf f sw = 1 mhz table 15-7. power fet driver ac specifications symbol description min typ max units notes t r rise time ? 45 55 ns c l = 4 nf t f fall time ? 45 55 ns t p(lh) propagation delay (low-to-high) ? ? 10 ns t p(hl) propagation delay (high-to-low)) ? ? 10 ns table 15-8. hysteretic controller dc specifications symbol description min typ max units notes v io comparator input offset voltage ? ? ? ? ? ? 7.5 10 15 mv mv mv 1 v ?? v icm ?? 3 v (industrial rated) 1 v ?? v icm ?? 3 v (extended temperature rated) 0 v ?? v icm ?? v dd v icm input common mode voltage range 0 ? v dd v v hys hysteresis voltage 4.5 4.5 ? ? 11 13 mv mv 1.5 v ? v icm ? 2.5 v (industrial rated) 1.5 v ? v icm ? 2.5 v (extended temperature rated) i shyst supply current - hyst eretic controller ? 2 ? ma includes two power peripheral comparators and one reference dac, f sw = 2 mhz table 15-9. hysteretic controller ac specifications symbol description min typ max units notes t on / t off minimum on/o ff timer [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 34 of 55 15.6 power peripheral comparator the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. monoshot<1:0> = 00 10 ? 30 ns monoshot<1:0> = 01 20 ? 60 ns monoshot<1:0> = 10 40 ? 110 ns monoshot<1:0> = 11 ? ? ? ns timers disabled table 15-9. hysteretic controller ac specifications symbol description min typ max units notes table 15-10. comparator dc specifications symbol description min typ max units notes v in input voltage range 0 ? v dd v v io comparator input offset voltage ? ? ? ? ? ? 7.5 10 15 mv mv mv 1 v ?? v icm ?? 3 v (industrial rated) 1 v ?? v icm ?? 3 v (extended temperature rated) 0 v ?? v icm ?? v dd v hys hysteresis voltage 2.5 4.5 4.5 ? ? ? 30 11 13 mv mv mv 0 v < v icm < v dd 1.5 v ? v icm ? 2.5 v (industrial rated) 1.5 v ? v icm ? 2.5 v (extended temperature rated) v ovdrv overdrive voltage 5 ? ? mv i scomp supply current - comparator ? ? 650 ? a v icm,comp comparator input common mode voltage range 0 ? v dd v table 15-11. comparator ac specifications symbol description min typ max units notes t d comparator delay time (fn0[x] pin to fn0[x] pin) ? 150 ? ns v ovdrv = 5 mv, c l = 10 pf at v dd = 5 v [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 35 of 55 figure 15-3. comparator timing diagram [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 36 of 55 15.7 power peripheral cu rrent sense amplifier the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to v dd of 5 v and hv dd of 32 v at 25 c. these are for design guidance only. figure 15-4. current sens e amplifier timing diagram table 15-12. current sense amplifier dc specifications symbol description min typ max units notes v icm input common mode voltage operating range 7 ? 32 v either terminal of the amplifier must not exceed this range for functionality v icm(tolerant) non functional operating range 0 ? 32 absolute maximum rating for v sense should never be exceeded. see absolute maximum ratings on page 29 v sense input differential voltage range 0 ? 150 mv i s,csa supply current - csa ? ? 1 ma enabling csa causes an incremental draw of 1 ma on the av dd rail. i biasp input bias current (+) ? ? 600 ? a i biasn input bias current (-) ? ? 1 ? a psr hv power supply rejection (csp pin) ? ? ?25 db f sw < 2 mhz k gain 19.7 19.4 20 20 20.3 20.6 v/v v/v v sense = 50 mv to 130 mv (industrial rated) v sense = 50 mv to 130 mv (extended temperature rated) v ios input offset ? 2 4 mv v sense = 50 mv to 130 mv c in_csp csp input capacitance ? ? 5 pf c in_csn csn input capacitance ? ? 2 pf table 15-13. current sense amplifier ac specifications symbol description min typ max units notes t settle output settling time to 1% of final value ? ? 5 ? s t powerup power up time to 1% of final value ? ? 5 ? s time out not valid v input -150 mv -50 mv 0v k*25 mv k* 100 mv v csp , v csn t powerup t settle t settle t delay t activate v csp v csn v input v input [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 37 of 55 15.8 power peripheral pwm/pr ism/dmm specification table the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. see the powerpsoc technical reference manual for more information on pwm/prism/dmm. table 15-14. pwm/prism/dmm dc specifications symbol description min typ max units notes i s,modulation supply current - pwm, prism, or dmm ? ? 5 ma table 15-15. pwm/prism/dmm ac specifications symbol description min typ max units notes pwm mode f range16 pwm output frequency range 16-bit period 24,000,000/(256*2 16 ) ? 48,000,000/2 16 hz period value = 2 16 ?1, min: n = 255, max: n = 0 f range8 pwm output frequency range 8-bit period 24,000,000/(256*2 8 ) ? 48,000,000/2 8 hz period value = 2 8 ?1, min: n = 255, max: n = 0 prism mode f range prism output frequency range 24,000,000/(256*(2 m ?1) ? 48,000,000/2 hz min: n = 255, maqx: n = 0, m = 2 to 16 dmm mode f range,dimming dmm dimming frequency range 24,000,000/ (256*max dmm period) ? 48,000,000/(mi n dmm period) hz min dmm period: 2 (right aligned), 3 (center aligned), 4(left aligned) max dmm period: 2 12 (right aligned), 8190 (center aligned), 2 12 (left aligned) f range,dither dmm dither frequency range (1/16)*(min f range,dimming) ? (15/16)*(max f range,dimming) hz [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 38 of 55 15.9 power peripheral refe rence dac specification the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. 15.10 power peripheral bu ilt-in switching regulator the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. table 15-16. reference dac dc specifications symbol description min typ max units notes i sdac supply current - reference dac ? ? 600 ? a mode 0 and mode1 inl integral non linearity ?1 ?1.5 ? ? 1 1.5 lsb lsb mode 0 mode 1 dnl differential non linearity ?0.5 ? 0.5 lsb mode 0 and mode1 a error gain error ?5 ?7 ? ? 5 7 lsb lsb mode 0 mode 1 os error offset error ? ? 1 lsb mode 0 and mode1 v dacfs fullscale voltage - reference dac ? ? ? ? 2.6 1.3 lsb lsb mode 0 mode 1 v dacmm fullscale voltage mi smatch (pair of reference dacs - even and odd) ? ? ? ? ? ? ? ? 9 14 10.5 15.5 lsb lsb lsb lsb mode 0 (dac0 through dac7) mode 1 (dac0 through dac7) mode 0 (dac8 through dac13) mode 1 (dac8 through dac13) table 15-17. reference dac ac specifications symbol description min typ max units notes t settle output settling time to 0.5 lsb of final value ? ? 10 ? s mode 0 and mode1 t startup startup time to within 0.5 lsb of final value ? ? 10.5 ? s mode 0 and mode1 table 15-18. built-in switching regulator dc specifications symbol description min typ max units notes v regin input supply voltage range 7 8 ? ? 32 32 v v industrial rated extended temperature rated see absolute maximum ratings on page 29 v regout output voltage range 4.8 5.0 5.2 v does not include v ripple v ripple output ripple ? ? 100 mv v uvlo under voltage lockout voltage 5.5 ? 6.5 v v regin < v uvlo : power down mode v regin > v uvlo : active mode i load dc output current -active mode 0.01 ? 250 ma i s,bsr supply current - built-in switching regulator ? ? 4 ma i sb,hv standby current (high voltage) ? ? 250 ? a i inrush inrush current ? ? ? ? 1.2 1.5 a a v regin = 32 v, sr regin = 32 v/ms (industrial rated) v regin = 32 v, sr regin = 32 v/ms (extended temperature rated) r ds(on),pfet pfet drain to source on resistance ? 2.5 ? ? line reg line regulation ? 1 ? mv i load = 250 ma, v regin = 7 v to 32 v [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 39 of 55 note if the built-in switching regulator is not being used in a design, it must be configured as per the following instructions to e nsure it is disabled in a safe state. sregfb: 5 v sregcsn: 5 v sregcsp: 5 v sregcomp: floating sreghvin: ? vdd rail sregsw: floating/tie to sreghvin if the switching regulator is disabled through wiring its input pi ns (as previously explained) t hen it must be disabled through software as well (bit sreg_tst[0] = 1), which is set in the gl obal resources in the interconnect view of psoc designer. load reg load regulation ? 1 ? mv v regin = 24 v, i load = 2.5 ma to 250 ma psrr power supply rejection ratio ? ?60 ? db v ripple = 0.2 * v regin, f ripple = 1 khz to 10 khz e bsr built-in switching regulator efficiency 80 ? ? % v regin = 24 v, i load = 250 ma table 15-19. built-in switching regulator ac specifications symbol description min typ max units notes f sw switching frequency 0.956 1 1.04 mhz t resp response time to within 0.5% of final value ? 10 ? ? s t su startup time ? ? 1 ms t pd power down time ? ? 100 ? s t pd_act time from power down to active mode ? ? 1 ms t act_pd time from active mode to power down mode ? ? 50 ? s sr regin ramp rate for the sreghvin pin ? ? 32 v/ ? s see absolute maximum ratings on page 29 table 15-20. built-in switching regulator recommended components component name value unit notes r fb1 2 k? tolerance 1% or better r fb2 0.698 k? tolerance 1% or better c comp 2200 pf tolerance 20% or better r comp 20 k? tolerance 5% or better l 47 ? h tolerance 20% or better, saturation current rating of 1.5 a or higher r sense 0.5 ? tolerance 1% or better c 1 10 ? f ceramic, x7r grade, minimum esr of 0.1 ? c in 1 ? f ceramic, x7r grade table 15-18. built-in switching regulator dc specifications [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 40 of 55 figure 15-5. built-in switching regulator timing diagram figure 15-6. built-in switching regulator v regin time powerdown mode t su v regout t pd t pd_act v regin 5 error amplifier comparator ref c in sregfb sregsw current sense amp sreghvin v regin sregcsp sregcsn osc logic and gate drive sregcomp v regout = 5 v 1 d l r sense c comp r comp c 1 r fb1 r fb2 esr v ss [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 41 of 55 15.11 general purpose i/o / function pin i/o the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. figure 15-7. gpio/function i/o timing diagram table 15-21. gpio/fn0 pin i/o dc specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, 80 ma maximum combined i oh budget v ol low output level ? ? 0.75 v i ol = 25 ma, 200 ma maximum combined i ol budget i oh high level source current 10 ? ? ma v oh = v dd ?1.0 v, see the limita- tions of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v v ih input high level 2.1 ? v v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a c in capacitive load on pins as input ? 3.5 10 pf t j = 25 c. c out capacitive load on pins as output ? 3.5 10 pf t j = 25 c. table 15-22. gpio/fn0 pin i/o ac specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns 10% ? 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 42 of 55 15.12 psoc core operational amplifier specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched capacitor psoc blocks. the guaranteed sp ecifications are measured in the analog continuous time psoc block. table 15-23. operational amplifier dc specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? 1.6 1.6 1.3 1.3 1.2 1.2 10 15 8 13 7.5 12 mv mv mv mv mv mv industrial rated extended temperature rated industrial rated extended temperature rated industrial rated extended temperature rated ? ? ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 ? v / c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 ? a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf t j = 25 c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? v dd v dd ? 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specifi- cation includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ? ? ? ? ? ? db db db v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high v dd ? 0.2 v dd ? 0.2 v dd ? 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated analog output buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 ? a ? a ? a ? a ? a ? a psrr oa supply voltage rejection ratio 52 80 ? db v ss ? v in ? (v dd ? 2.25) or (v dd ? 1.25 v) ? v in ? v dd . [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 43 of 55 15.13 psoc core low power comparator the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. table 15-24. operational amplifier ac specifications symbol description min typ max units notes t roa rising settling time from 80% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 ? s ? s ? s t soa falling settling time from 20% of ? v to 0.1% of ? v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 ? s ? s ? s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s sr foa falling slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/r-hz table 15-25. low power comparator dc specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd ? 1 v i slpc lpc supply current ? 10 40 ? a v oslpc lpc voltage offset ? 2.5 40 mv table 15-26. low power comparator ac specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 ? s ? 50 mv overdrive comparator reference set within v reflpc . [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 44 of 55 15.14 psoc core analog output buffer the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. table 15-27. analog output buffer dc specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? ? 3 3 12 18 mv mv industrial rated extended temperature rated tcv osob average input offset voltage drift ? +6 ? ? v/c v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 0.6 0.6 ? ? ? ? v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 x v dd + 1.1 0.5 x v dd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to v dd /2) power = low power = high ? ? ? ? 0.5 x v dd ? 1.3 0.5 x v dd ? 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 52 64 ? db (0.5 x v dd ? 1.3) ? v out ? (v dd ? 2.3). table 15-28. analog output buffer ac specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.5 2.5 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.2 2.2 ? s ? s [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 45 of 55 sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s bw obss small signal bandwidth, 20 mv pp , 3 db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1 v pp , 3 db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 15-28. analog output buffer ac specifications symbol description min typ max units notes [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 46 of 55 15.15 psoc core analog reference the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. the guaranteed specificat ions are measured through the anal og continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power leve ls for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. 15.16 psoc core analog block the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. table 15-29. analog reference dc specifications symbol description min typ max units notes bg bandgap voltage reference 1.28 1.27 1.30 1.30 1.32 1.33 v v industrial rated extended temperature rated ? agnd = v dd /2 [15] v dd /2 ? 0.04 v dd /2 ? 0.02 v dd /2 ? 0.01 v dd /2 v dd /2 + 0.007 v dd /2 + 0.02 v v industrial rated extended temperature rated ? agnd = 2 x bandgap [15] 2 x bg ? 0.048 2 x bg ? 0.030 2 x bg + 0.024 v ? agnd = bandgap [15] bg ? 0.009 bg + 0.008 bg + 0.016 v ? agnd = 1.6 x bandgap [15] 1.6 x bg ? 0.022 1.6 x bg ? 0.010 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = v dd /2) [15] ?0.034 0.000 0.034 v ? refhi = v dd /2 + bandgap v dd /2 + bg ? 0.10 v dd /2 + bg v dd /2 + bg + 0.10 v ? refhi = 3 x bandgap 3 x bg ? 0.06 3 x bg 3 x bg + 0.06 v ? refhi = 3.2 x bandgap 3.2 x bg ? 0.112 3.2 x bg 3.2 x bg + 0.076 v ? reflo = v dd /2 ? bandgap v dd /2 ? bg ? 0.04 v dd /2 ? bg ? 0.06 v dd /2 ? bg + 0.024 v dd /2 ? bg v dd /2 ? bg + 0.04 v dd /2 ? bg + 0.06 v v industrial rated extended temperature rated ? reflo = bandgap bg ? 0.06 bg bg + 0.06 v table 15-30. analog block dc specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k? c sc capacitor unit value (switched capacitor) ? 80 ? ff notes 15. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3 v 0.02 v. [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 47 of 55 15.17 psoc core por and lvd the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. note the bits porlev and vm in the following table refer to bits in the vlt_cr register. see the powerpsoc technical reference manual for more information on the vlt_cr register. 15.18 psoc core programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. table 15-31. por and lvd dc specifications symbol description min typ max units notes v ppor2 v dd value for ppor trip porlev[1:0] = 10b ? 4.55 4.70 v v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 110b vm[2:0] = 111b 4.62 4.71 4.73 4.81 4.83 4.95 v v table 15-32. programming dc specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 15 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during prog ramming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during prog ramming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? v ss + 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [16] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention [17] 10 ? ? years notes 16. a maximum of 36 x 50,000 block endurance cycles is allowed. th is may be balanced between operations on 36 x 1 blocks of 50,0 00 maximum cycles each, 36 x 2 blocks of 25,000 maximum cycles each, or 36 x 4 blocks of 12, 500 maximum cycles each (to limit the total number of cycles to 36 x 50,000 and that no single block ever sees more than 50,000 cycles) 17. guaranteed for ?40 c ? t a ? 85 c for industrial rated devices and ?40 c ? t a ? 105 c for extended temperature rated devices. [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 48 of 55 15.19 psoc core digita l block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. table 15-33. programming ac specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 50 ns t eraseall flash erase time (bulk) ? 40 ? ms erase all blocks and protection fields immediately t program_hot flash block erase + flash block write time ? ? 100 [18] ms 0 c ? tj ? 100 c t program_cold flash block erase + flash block write time ? ? 200 [18] ms ?40 c ? tj ? 0 c table 15-34. digital block ac specifications function description min typ max units notes timer capture pulse width 50 [19] ? ? ns maximum frequency, no capture ? ? 49.92 mhz maximum frequency, with capture ? ? 24.96 mhz counter enable pulse width 50 [19] ? ? ns maximum frequency, no enable input ? ? 49.92 mhz maximum frequency, enable input ? ? 24.96 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [19] ? ? ns disable mode 50 [19] ? ? ns maximum frequency ? ? 49.92 mhz crcprs (prs mode) maximum input clock frequency ? ? 49.92 mhz crcprs (crc mode) maximum input clock frequency ? ? 24.96 mhz spim maximum input clock frequency ? ? 8.32 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.16 mhz width of ss_ negated between transmissions 50 [19] ? ? ns transmitter maximum input clock frequency maximum input clock frequency with v dd ?? 4.75 v, 2 stop bits ? ? ? ? 24.96 49.92 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. notes 18. for the full industrial range, you must employ a temperature s ensor user module (flashtemp) and feed the result to the tempe rature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 19. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 49 of 55 15.20 psoc core i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v, t j ? 115 c for industrial rated devices and 4.75 v to 5.25 v, t j ? 125 c for extended temperature rated devices. typical parameters apply to 5 v at 25 c. these are for design guidance only. figure 15-8. definition of timing for fast/standard mode on the i 2 c bus receiver maximum input clock frequency maximum input clock frequency with v dd ?? 4.75 v, 2 stop bits ? ? ? ? 24.96 49.92 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. table 15-34. digital block ac specifications table 15-35. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s t highi2c high period of the scl clock 4.0 ?0.6 ? ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data setup time 250 ?100 [20] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns note 20. a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t sudati2 ? 250 ns must then be met. this is automatically the case if the device does not stretch the low peri od of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line trmax + t sudati2 = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 50 of 55 16. ordering information 16.1 ordering code definitions table 16-1. device key features and ordering information powerpsoc part number no. of pins package channels voltage internal fets gate drivers for external low side n-fets cy8cled04d01-56ltxi 56 qfn 8 mm x 8 mm 4 32 v 4 x 1.0 a 4 CY8CLED04D02-56ltxi 56 qfn 8 mm x 8 mm 4 32 v 4 x 0.5 a 4 cy8cled04g01-56ltxi 56 qfn 8 mm x 8 mm 4 32 v 0 4 cy8cled04docd1-56ltxi 56 qfn 8 mm x 8 mm 4 32 v 4 x 1.0 a 4 cy8cled03d01-56ltxi 56 qfn 8 mm x 8 mm 3 32 v 3 x 1.0 a 3 cy8cled03d02-56ltxi 56 qfn 8 mm x 8 mm 3 32 v 3 x 0.5 a 3 cy8cled03g01-56ltxi 56 qfn 8 mm x 8 mm 3 32 v 0 3 cy8cled02d01-56ltxi 56 qfn 8 mm x 8 mm 2 32 v 2 x 1.0 a 2 cy8cled01d01-56ltxi 56 qfn 8 mm x 8 mm 1 32 v 1 x 1.0 a 1 cy8cled01d01-56ltxq 56 qfn 8 mm x 8 mm 1 32 v 1 x 1.0 a 1 cy 8 c led0x xxx (xxxx) - xx xxxx package type: thermal rating: ltx=qfn pb-free i = industrial q = extended temperature pin count ocd1 = on chip debugger part number: d01 = internal 1.0 a fets, d02 = internal 0.5 a fets, g01 = no internal fets family code: 4 = 4 channel, 3 = 3 channel, 2 = 2 channel, 1 = 1 channel technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 51 of 55 17. packaging information packaging dimensions this section illustrates the package specification for t he cy8cled04d0x, cy8cled04g01, cy8cled03d0x, cy8cled03g01, cy8cled02d01, and cy8cled01d01 along with the thermal impedance for the package a nd solder reflow peak temperatures. important note for information on the preferred dimensions for mount ing qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf. figure 17-1. 56-pin (8x8 mm) qfn 17.1 thermal impedance 17.2 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 51-85187 *e package typical ? ja [21] 56 qfn [22] 16.6 c/w package minimum peak temperature [23] maximum peak temperature 56 qfn 240 c 260 c notes 21. t j = t a + power x ? ja 22. to achieve the thermal impedance specified for the qfn package, the center thermal pad should be soldered to the pcb ground plane. 23. higher temperatures may be required based on the solder melting po int. typical temperatures for solder are 220 5 c with s n-pb or 245 5 c with sn-ag-cu paste refer to the solder manufacturer specifications. [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 52 of 55 18. acronyms 19. document conventions 19.1 units of measure acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit csa current sense amplifier ct continuous time dac digital-to-analog converter dali digital addressable lighting interface dc direct current dmm delta sigma modulation mode dmx digital multiplexing dsm delta sigma modulator dtmf dual-tone multi frequency eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference faq frequently asked questions fet field effect transistor fsr full scale range gpio general purpose i/o gui graphical user interface hbm human body model ic integrated circuit ice in-circuit emulator ide integrated development environment ilo internal low-speed oscillator imo internal main oscillator issp in-system serial programming i/o input/output ipor imprecise power on reset led light emitting diode lsb least-significant bit lvd low voltage detect mcu microcontroller mosfet metal-oxide-semiconductor field effect transistor msb most-significant bit ocd on chip debugger pc program counter por power on reset ppor precision power on reset powerpsoc power programmable system-on-chip? prism precise intensity signal modulation psoc programmable system-on-chip? pwm pulse width modulator qfn quad flat no leads package rgba red, green, blue, amber rggb red, green, green, blue sar successive approxi mation register sc switched capacitor scl serial i 2 c sclk serial issp clock sda serial i 2 c data sdata serial issp data spi serial peripheral interface sram static random access memory trm technical reference manual uart universal asynchronous receiver/transmitter usb universal serial bus wdt watch dog timer symbol unit of measure c degrees celsius db decibels hz hertz pp peak-to-peak ? sigma:one standard deviation v volts ? ohms kb 1024 bytes ppm parts per million sps samples per second w watts a amperes kbit 1024 bits khz kilohertz k? kilohms mhz megahertz m? megaohms ? a microamperes ? f microfarads ? h microhenrys ? s microseconds ? v microvolts ? vrms microvolts root-mean-square acronym description [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 53 of 55 ? w microwatts ma milliampere ms millisecond mv millivolts mw milliwatts na nanoamperes ns nanoseconds nv nanovolts pa picoamperes pf picofarads ps picoseconds ff femtofarads symbol unit of measure [+] feedback
cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 document number: 001-46319 rev. *n page 54 of 55 20. document history page document title: cy8cled04d01, CY8CLED04D02, cy8cle d04g01, cy8cled03d01, cy8cled03d02, cy8cled03g01, cy8cled02d01, cy8cled01d01 powerpsoc ? intelligent led driver document number: 001-46319 revision ecn no. orig. of change submission date description of change ** 2506500 anwa/ dsg 05/20/08 new datasheet. *a 2575708 anwa/ aesa 10/01/08 1) updated logic block diagr am with ainx label and sregfb pin. 2) updated current sense am plifier specification table. 3) updated external gate driver specification table. 4) updated register table. *b 2662774 kjv 02/19/09 extensive changes made to content and electrical specifications. *c 2665155 kjv/pyrs 02/25/09 updated note s in electrical specifications. *d 2671254 kjv/pyrs 03/10/09 updated sections 8, 9, and 10 on pages 14, 15, and 16. *e 2683506 ved 04/03/09 release to the external web site. *f 2698529 kjv/pyrs 04/27/09 updated figure 15-2. , and figure 15-4. . *g 2735072 kjv 07/10/09 added 1 and 2 channel part information. *h 2765369 kjv 09/17/09 updated electrical specifications. *i 2870389 fre/pyrs 02/01/10 ad ded table of contents updated absolute maximum ratings, dc gpio, ac chip-level, and ac programming specifications as follows: added v reginmax absolute maximum specification. modified t write specification. added i oh , i ol , dc ilo , f 32k_u , t powerup , t eraseall , t program_hot , and t program_cold specifications updated package diagram *j 2952677 fre/ukk 06/15/10 datasheet reviewed and updated with a view to improve clarity, readability and customer-friendliness. this includes language, consistency in terminology to match software and other powerpsoc documentation, changes to reflect major changes in software such as removal of system level design addition of links to relevant collateral such as kits, technical reference manuals and application notes. *k 3031567 fre/ukk 09/16/10 removed dali in page 1 a nd page 13, and added the dali note in page 13. added a note to section 15.10 after table 15-20 on page 38. updated as per the new cypress style and datasheet template. *l 3073506 kjv 11/08/2010 updated datasheet to add extended temperature rated device cy8cled01d01-56ltxq *m 3178540 kjv 02/28/2011 updated certain specificat ions for extended temperature rated device *n 3244595 kjv 05/04/2011 updated description for symbol v regin and v csp, v csn in ta b l e 1 4 - 1 . updated figure 15-6. [+] feedback
document number: 001-46319 rev. *n revised may 4, 2011 page 55 of 55 psoc designer?, programmable system-on-chip?, and prism? are trademarks and psoc? and, powerpsoc? are registered trademarks of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. cy8cled04d01, cy8cle d04d02, cy8cled04g01 cy8cled03d01, cy8cle d03d02, cy8cled03g01 cy8cled02d01, cy8cled01d01 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 21. sales, solutions , and legal information 21.1 worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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